---
# System prepended metadata

title: Lab 9

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# Lab 9
Name: SUDDULA VINEETH RAGHAVENDRA
Roll No.: CS22B045

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## Question 1
**Verilog Code for basic Arithmetic and Logical Unit(ALU) which takes 2 inputs and produces an output.**

```
module alu(input [1:0] op, 
           input [3:0] A,  
           input [3:0] B,  
           output reg [3:0] result); 

   wire [3:0] add_out,sub_out,and_out,or_out; 
   // here op is a 2-bit input that selects the operation to be performed.
   // here A and B are 4-bit inputs.
   // here result is a 4-bit output that stores the result of the selected operation.
   
   assign add_out = A+B;   
   assign sub_out = A-B;   
   assign and_out = A&B;
   assign or_out = A|B;
   
   mux mux1(.I0(add_out),.I1(4'b0),.S(op == 2'b00),.Y(result));
   mux mux2(.I0(sub_out),.I1(4'b0),.S(op == 2'b01),.Y(result));
   mux mux3(.I0(and_out),.I1(4'b0),.S(op == 2'b10),.Y(result));
   mux mux4(.I0(or_out),.I1(4'b0),.S(op == 2'b11),.Y(result)); 
endmodule

module mux(I0,I1,S,Y); // this is the code for the multiplexer.
input I0,I1,S;
output Y;
assign Y = S?I1:I0;   
endmodule

```

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## Question 2

**Verilog code for a simple 8 bit processor capable of load and store operation.**

```
module simple_processor (
    input [7:0] instruction
);

    reg [7:0] memory [255:0]; // 256 bytes of memory
    reg [7:0] reg_file [15:0]; // 16 general-purpose 8-bit registers
    
    // Extracting information which is required from the instruction
    reg [1:0] operation;
    reg [3:0] dest_reg;
    reg [2:0] offset;
    reg [3:0] base_reg;

    assign operation = instruction[7:6];
    assign dest_reg = instruction[5:2];
    assign offset = instruction[4:2];
    assign base_reg = instruction[1:0];

    // Performing the lw and sw operations depending upon the instruction.
    // here we assumed operation to be 2 bit so we are assuming that 00 is considered for the lw operation and 01 is for sw operation.
    always @(*) begin
        if (operation == 2'b00) begin // Load (lw) operation
            reg_file[dest_reg] = memory[reg_file[base_reg] + offset];
        end
        else if (operation == 2'b01) begin // Store (sw) operation
            memory[reg_file[base_reg] + offset] = reg_file[dest_reg];
        end
    end
endmodule

```

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## Question 3
**Code**

```
#include <stdio.h>
int main(){
        int a =5,b=4;
        printf("%d",a+b);
        return 0;
}
```

**inscount.log**
the value is 133725

**Output**
![lab9](https://hackmd.io/_uploads/rkKjuo-xA.jpg)


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