# 計算機組織 Ch.5 Large and Fast: Exploiting Memory Hierarchy (C)
###### tags: `計算機組織`, `109-2`

[TOC]

## Virtual Memory (5-7) ==IMPORTANT==

### Virtual Memory
- 解釋：把 Main Memory 當作硬碟的 Cache
- 所有程式共享一個 Main Memory
- 由 CPU 本身與 OS 共同管理
- 他們會把 Main Memory 分配成多塊，Map 成 Virtual Memory
- 每個程式會拿到他相應的 Virtual Memory
- 不能超出自己的範圍
- Virtual Mamory 與 Physical Memory
- "Block" 在 VM 被稱作 "Page"
- "Miss" 被稱作 "Page Fault"


### Page Fault Penalty
- 當發生 Page Fault，那個 Page 就必須要重新去跟硬碟拿
- 由 OS 去處理
- 會花費大量 Clock Cycle (數以百萬計)
- 如何降低 Page Fault 的發生率？
- Fully-Associative
- Smart Replacement Algorithms

### Page Tables
- 存放資訊
- **Page Table Entries (PTE)** (Indexed by virtual page number (per process))
- **Page table register** in CPU: points to page table in physical memory
- If Page is present in Memory
- PTE (page table entry) stores the physical page number
- and other status bits (referenced, dirty, …)
- Else...
- PTE can refer to location in swap space on disk


### Replacement and Writes
- 為了減少 Page Fault，偏好 LRU (Recently Used) Replacement (EXPENSIVE!)
- 每次讀取 Page 時，Reference Bit (AKA Use Bit) in PTE 設為 1
- 定期被 OS 清 0
- 所以，我們可以用以判斷哪些 Bit 最近有被用過
- 硬碟寫入會花大量時間
- Use block, not individual
- Use WB (Write Back)
- 當 Page 被寫入，設定 "Dirty Bit" (in PTE)

## Fast Translation using TLB
- Address Translation 看起來會花更多 Memory Reference
- 1 個用以存取 PTE
- 1 個存實際記憶體區
- 但是能夠提升 Locality
### **Translation Look-Aside Buffer (TLB)**
- works as a **cache to the page table**
- Typical: 16–512 PTEs, 0.5–1 cycle for hit, 10–100 cycles for miss, 0.01%–1% miss rate
- Misses could be handled by hardware or software


#### TLB Hit
- TLB hit on Read
- TLB hit on write
- Toggle dirty bit (write back to page table on replacement)

#### TLB Miss
- If page is in memory
- Load the PTE from memory and Retry
- 這個程序可以由硬體或軟體達成
- Must recognize TLB miss before destination register overwritten
- If page is not in memory (PAGE FAULT)
- OS 去拿 Page 並更新
- 利用 Faulting Virtual Address 去找 PTE
- 找到 Page 相應硬碟位置
- 選擇要替換的 Page
- 如果那個 Page 被標記為 Dirty，先寫入
- 讀入 Page 並更新 Page Table
- 然後重啟 Faulting Instruction，讓 Process 繼續跑


### TLB and Cache Interaction //IMPORTANT
- 如果 cache 的 TAG 用的是實體位置 (Physical)
- 要先轉譯再進行查表
- Alternative: use virtual address tag
- Complications due to aliasing: 不同 virtual addresses 可能會有相同 physical address
- Note, processors may overlap translation with cache access



## A Common Framework for Memory Hierarchies (5-8)

### Review: Cache Design Trade-off