---
# System prepended metadata

title: Trip to US
tags: [Others]

---

# Trip to US

###### Tags: `Others`

## 01/11/2019

### 1. <span style="color: #1f78b4">LHR (01/11/2019 16:15) -> SFO (01/11/2019 20:20)</span> <span style="color: #e41a1c">[C8R3LI]</span>
### 2. <span style="color: #1f78b4">SFO (01/11/2019 20:20) -> Embassy Suites Santa Clara 2885 Lakeside Dr Santa Clara, CA 95054</span> <span style="color: #e41a1c">[2349257]</span>

<details>
  <summary><span style="font-size:0.8em;color: #b15928">Special Instructions</span></summary>
  Claim your luggage, follow signage for Shared Ride Vans & exit the terminal through the Arrivals (lower) level. For T1 exit door #15, for T2 & International exit door #4, and for T3 exit door #1. Proceed outside to the center island for all terminals. A SuperShuttle representative in a blue jacket will be available on the center island for assistance from 8am until midnight. After hours please call for (650) 588-2442 for dispatch.
</details>

## 02/11/2019

### Informal meetings with Theo Drane (Intel) and Sam Bayliss (Xilinx) - it's a Saturday, so probably not at the company

<!--- 

Abstract:

Given the ever increasing demands on verification and validation in the face of shrinking times to market, systemic complexity and the drive for increasingly robust and reliable IP generation – verification engineers are favouring formal techniques over more traditional constrained random testing. This talk will explore the ways in which Imagination Technologies has been adopting word-level formal equivalency checking, initially focussing on datapath. We have pushed the tools to perform property as well as equivalency checking and we continue to push the envelope in terms of application.

Biography:

Theo Drane started working for the datapath consultancy Arithmatica in 2002 after completely a Mathematics degree from the University of Cambridge, UK. He moved to Imagination Technologies in 2005 where his interests are datapath optimisation, verification and validation.

After a two year sabbatical to work for an independent financial provider, Markit, he returned to Imagination to head up their datapath team while studying for a PhD at Imperial College London

Verification Futures Conference Presentation Not Available

--->

## 03/11/2019

### 1. TPC meeting of FPGA 2020 

My paper number is 15.

### 2. <span style="color: #1f78b4">SJC (03/11/2019 18:00) -> Asilomar Conference Grounds Pacific Grove, 800 Asilomar Ave</span> <span style="color: #e41a1c">[MA5586938]</span>

<details>
  <summary><span style="font-size:0.8em;color: #b15928">SJC Domestic Arrivals</span></summary>
Terminal A:
Exit curbside from baggage claim, turn left/south to sign post on curb labeled ‘Scheduled Buses’ Bus stop 4 - about 30 to 50 yards (just past the private car pick-up zone).

http://www.montereyairbus.com/san-jose-terminala

Terminal B: Across the street from baggage claim to the ground transportation island shelter labeled ‘Scheduled Buses’. Bus stop #10
http://www.montereyairbus.com/san-jose-terminalb
</details>

### 3. Asilomar Schedule

<details>
  <summary><span style="font-size:0.8em;color: #b15928"> Schedule Links </span></summary>
  
Asilomar: http://asilomarssc.org/
Technical chedule at: https://www2.securecms.com/Asilomar2019/RegularProgram.asp
</details>

15:00 - 19:00 Registration (Merrill Hall)
16:00 - 18:00 Student Paper Contest (Merrill Hall)
17:00 - 18:00 Keynote: Nikos Sidiropoulos - *Canonical Identification: A Principled Alternative to Neural Networks* (Nautilus)
19:00 - 21:00 Welcoming Reception (Merrill Hall)

## 04/11/2019

<details>
  <summary><span style="font-size:0.8em;color: #b15928"> Schedule Links </span></summary>
  
Asilomar: http://asilomarssc.org/
Technical chedule at: https://www2.securecms.com/Asilomar2019/RegularProgram.asp
</details>

[My print-friendly schedule 04/11](https://hackmd.io/TMccYcdmQ2uzhpN8mWh_dA)

<!---

Paper:	MA6b-3
Session:	Compilation for Spatial Computing Architectures (Invited)
Location:	Toyon
Session Time:	Monday, November 4, 10:15 - 11:55
Presentation Time:	Monday, November 4, 11:05 - 11:30
Presentation:	Oral
Topic:	Architectures and Implementation: Reconfigurable Processing
Paper Title:	Analysis Methods for Memory in High-Level Synthesis
Authors:	George Constantinides, Imperial College London, United Kingdom

-->

## 05/11/2019

<details>
  <summary><span style="font-size:0.8em;color: #b15928"> Schedule Links </span></summary>
  
Asilomar: http://asilomarssc.org/
Technical chedule at: https://www2.securecms.com/Asilomar2019/RegularProgram.asp
</details>

[My print-friendly schedule 05/11](https://hackmd.io/P_J6I3LDRLiJDmhgD2kukw)

## 06/11/2019

### 1. Asilomar Schedule

<details>
  <summary><span style="font-size:0.8em;color: #b15928"> Schedule Links </span></summary>
  
Asilomar: http://asilomarssc.org/
Technical chedule at: https://www2.securecms.com/Asilomar2019/RegularProgram.asp
</details>

[My print-friendly schedule 06/11](https://hackmd.io/1b3mIQvkQdmMqfUvMiVuWw)


### 2. <span style="color: #1f78b4">MRY (06/11/2019 14:02) -> LAX (06/11/2019 15:26)</span> <span style="color: #e41a1c">[C8R3LI]</span>

## 07/11/2019

### Visit to UCLA to see Jason Cong and Miloš Ercegovac

12:00-1:00pm George, Jianyi & James with Miloš in Miloš's office

1:00-3:30pm George, Jianyi & James to meet Jason's PhD students - Jason's PA to advise where

3:30pm-4:00pm Free - maybe get a coffee with Miloš?

4:00pm-5:00pm (about) George's seminar

5:00pm-6:00pm Free

6:00pm George to have Dinner with Miloš, Jason's students are organizing something for James and Jianyi (Miloš thinks)

---

10:30am-12:00pm	Discussions with Miloš, maybe also walking tour of UCLA campus  

12:00-1:00pm	Lunch at Faculty Center with Prof. Ercegovac
  
  1:00-1:30pm	Meet with Jie Wang, Graduate Student Researcher

  1:30-2:00pm	Meet with Young-kyu Choi, Postdoc Scholar

  2:00-2:30pm	Meet with Atefeh Sohrabizadeh, Graduate Student Researcher

  2:30-3:00pm	Meet with Zhe Chen, Postdoc Scholar
 
  3:00-3:30pm	Meet with Weikang Qiao, Graduate Student Researcher

  3:45-4:15pm	Refreshments for CS 201 seminar, 3400 Boelter Hall

 4:15-5:45pm	CS 201 Seminar, Rethinking Hardware Accelerators for Deep Neural Networks, Prof. Constantinides, 3400 Boelter Hall


## 08/11/2019

### <span style="color: #1f78b4">LAX (08/11/2019 15:00) -> LHR (09/11/2019 09:20)</span> <span style="color: #e41a1c">[C8R3LI]</span>

## Remarks


