---
# System prepended metadata

title: Write a FIFO in SV

---

# Write a FIFO in SV

```systemverilog
xxx

module fifo(
    clock,
    reset,
    data_in,
    read_en,
    data_out,
    write_en,
    full,
    empty)
    
    logic [7:0] array [7:0];
    
    always_ff @(posedge clock)
        if(read_en == 1'b1)
            array[0] <= data_in;
            
            

```