---
# System prepended metadata

title: Trip to US 21022020
tags: [Others]

---

# Trip to US 21022020

###### tags: `Others`

## FPGA Conference

##### <span style="color: #1f78b4"> Feb 21 Departure </span>

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1. 【EKSWYG】VS41 LHR 16:15 to SFO 19:20 
2. 【MA6006472】Monterey Airbus 20:30 - Cross the street from customs exit (door #1) to the sign post on the center island labeled ‘Airporters’.
3. 【80686452】Embassy Suites Seaside, 1441 Canyon Del Rey

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##### <span style="color: #1f78b4"> Feb 22 SpatialML</span>

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9:15am Arrival and Coffee
9:30am George Constantinides, Imperial College: Introduction to the Day
9:40am Jason Anderson, UofT, CGRA-ME: A Modelling and Evaluation Platform for Coarse-Grained Spatial Architectures
10:00am Miloš Ercegovac, UCLA, Left-to-Right Arithmetic Paradigm: Computing while Communicating - Terminate Gracefully at Any Moment
10:20am Mike Hutton, Google: Accelerating Deep Learning with Tensor Processing Units
10:40am Geoff Merrett, Southampton: Optimising Resource Management for Embedded Machine Learning
11:00am Vaughn Betz, UofT: Optimizing ML on FPGAs with a New Accelerator Style and Architecture Changes  and Incorporating Learning in FPGA Placement
11:20am Christos Bouganis, Imperial:  Deploying CNNs in the embedded space
11:40am Coffee
12:00pm Ram Krishnamurthy, Intel: AI and machine learning accelerator challenges and opportunities in sub-7nm technologies
12:20pm Jason Cong, UCLA: Automatic compilation of systolic arrays to FPGAs
12:40pm Sam Bayliss, Xilinx: An MLIR-based compiler for Xilinx AI Engine
1:00pm Lunch – buffet lunch will be provided at the hotel
1:40pm Jon Hare, Southampton: Optimising deep nets to fit the hardware and energy constraints: taking inspiration from biology
2:00pm Wayne Luk, Imperial College: Custom Computing for Deep Learning Research
2:20pm Naif Tarafdar, UofT, AIgean: An Open Framework for Machine Learning on Heterogeneous Clusters
2:40pm George Constantinides, Imperial College. Learning Arithmetic: Boolean Topologies for Deep Learning
3:00pm Bryan Catanzaro, NVIDIA: Title TBC
3:20pm Coffee + Research Clustering Activity (identification of research commonality)
4:00pm Research Cluster Discussions (planning concrete researcher exchange and collaboration possibilities)
4:50pm Plenary Feedback from Cluster Discussions
5:20pm George Constantinides, Imperial College: Next Steps
5:30pm End of formal sessions
6:00pm Dinner – dinner will be provided at the hotel

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##### <span style="color: #1f78b4"> Feb 23 FPGA </span>

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8:00 Session: Invited Tutorials
8:00	Vitis Introduction: Edge and Cloud Acceleration Workflow
Parimal Patel
8:30	From C/C++ to Dynamically Scheduled Circuits
 Lana Josipović (EPFL), Andrea Guerrieri (EPFL); Paolo Ienne (EPFL)
9:30	FPGA Hardware Security for Datacenters and Beyond
Kaspar Matas(The University of Manchester); Tuan La(The University of Manchester); Nikola Grunchevski(The University of Manchester); Khoa Pham(The University of Manchester); Dirk Koch(University of Manchester)
11:30	Lunch
12:45	Invited Session: Security in FPGA Design and Application (Chair: Ryan Kastner, University of California, San Diego; and Russell Tessier, University of Massachusetts)
12:45	Establishing trust in Microelectronics
Lee Lerner (Georgia Tech)
13:00	Thermal and Voltage Side Channels and Attacks in Cloud FPGAs
Jakub Szefer (Yale University)
13:15	Multi-tenant FPGA Security: Challenges and Opportunities
Patrick Koeberl (Intel Corporation)
13:30	FPGA/SoC Security: Arms Race in the Cloud
Steve McNeil (Xilinx)
13:45	Panel Discussion
14:15	Coffee Break
14:30	Invited Panel: What to do with Datacenter FPGAs Besides Deep Learning (Chair: Andrew Putnam, Microsoft)
16:00	Close for the day
16:00	FCCM PC Meeting
19:30	Reception
<span style="color: #e41a1c">Having dinner with Lana and Paolo</span>


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##### <span style="color: #1f78b4"> Feb 24 FPGA </span>

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8:00	Open the conference (General Chair/Program Chair)
8:15	Keynote: Symbiosis in Action: Reconfigurable Architectures and EDA (Chair: Lesley Shannon, Simon Fraser University)
Mahesh Iyer (Intel)
8:45	Session: High-Level Abstractions and Tools I (Chair: Caiwen Ding, University of Connecticut)
8:45	Maximizing the Serviceability of Partially Reconfigurable FPGA Systems in Multi-tenant Environment
Tuan D. A. Nguyen(Technische Universität Dresden); Akash Kumar(Technische Universitaet Dresden)
9:10	AutoDNNchip: An Automated DNN Chip Generator through Compilation, Optimization, and Exploration
Pengfei Xu(Rice University); Yang Zhao(Rice University); Xiaofan Zhang(University of Illinois at Urbana-Champaign); Cong Hao(University of Illinois Urbana-Champaign); Zetong Guan(Rice University); Yongan Zhang(Rice University); Yue Wang(Rice University); Deming Chen(University of Illinois Urbana-Champaign); Yingyan Lin(Rice University)
9:35	HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration
Jiajie Li(Tsinghua University); Yuze Chi(University of California, Los Angeles); Jason Cong(UCLA)
9:40	Fingerprinting Cloud FPGA Infrastructures
Shanquan Tian(Yale University); Wenjie Xiong(Yale University); Ilias Giechaskiel(University of Oxford); Kasper Rasmussen(University of Oxford); Jakub Szefer(Yale University)
9:45	Poster Session I (Chair: Vaughn Betz, University of Toronto)
10:55	Session: Appications I (Chair: Miriam Leeser, Northeastern University)
10:55	Massively Simulating Adiabatic Bifurcations with FPGA to Solve Combinatorial Optimization
Yu Zou(University of Central Florida); Mingjie Lin(University of Central Florida)
11:20	High-performance FPGA network switch architecture
Philippos Papaphilippou(Imperial College London); Jiuxi Meng(Imperial College London); Wayne Luk(Imperial College)
11:45	Using OpenCL to Enable Software-like Development of an FPGA-Accelerated Biophotonic Cancer Treatment Simulator
Tanner Young-Schultz(University of Toronto); Lothar Lilge(Princess Margaret Cancer Centre); Stephen Brown(University of Toronto); Vaughn Betz(University of Toronto)
12:10	Energy-Efficient 360-Degree Video Rendering on FPGA via Algorithm-Architecture Co-Design
Qiuyue Sun (University of Rochester); Amir Taherin(University of Rochester); Yawo Siatitse(University of Rochester); Yuhao Zhu (University of Rochester)
12:15	Real-Time Spatial 3D Audio Synthesis on FPGAs for Blind Sailing
Anish Singhani(Olin College of Engineering); Alexander Morrow(Olin College of Engineering)
12:20	Lunch
13:45	Session: Deep Learning I (Chair: Bita Rouhani, Microsoft)
13:45	When massive GPU parallelism ain’t enough: A Novel Hardware Architecture of 2D-LSTM Neural Network
Vladimir Rybalkin(University of Kaiserslautern); Norbert Wehn(University of Kaiserslautern)
14:10	Light-OPU: An FPGA-based Overlay Processor for Lightweight Convolutional Neural Networks
Yunxuan Yu(Rednova Innovations Inc); Tiandong Zhao(Rednova Innovations Inc); Kun Wang(Rednova Innovations Inc); Lei He(ECE department, UCLA)
14:35	End-to-End Optimization of Deep Learning Applications
Atefeh Sohrabizadeh(University of California Los Angeles); Jie Wang(UCLA); Jason Cong(UCLA)
14:40	Poster Session II (Chair: Mike Hutton, Google)
15:50	Session: FPGA Architecture (Chair: Satwant Singh, Lattice Semiconductor Corp)
15:50	Architectural Enhancements in Intel Agilex FPGAs
Jeff Chromczak(Intel); Mark Wheeler(Intel); Charles Chiasson(Intel); Dana How(Intel); Martin Langhammer(Intel); Tim Vanderhoek(Intel); Grace Zgheib(Intel Corporation); Ilya Ganusov(Intel)
16:15	Straight to the Point: Intra- and Inter-Cluster LUT Connections to Mitigate the Delay of Programmable Routing
Stefan Nikolic(EPFL); Grace Zgheib(Intel Corporation); Paolo Ienne(EPFL)
16:40	LUXOR: An FPGA Logic Cell Architecture for Efficient Compressor Tree Implementations
Seyedramin Rasoulinezhad(University of Sydney); Siddhartha -(University of Sydney); Hao Zhou(Fudan University); Lingli Wang(Fudan University); David Boland(University of Sydney); Philip H.W. Leong(University of Sydney)
17:05	Steering Committee Meeting
18:30	Dinner
Panel (Chair: Raymond Nijssen, Achronix)
FPGAs will never be the same again:  How the newest FPGA architectures are totally disrupting the entire FPGA ecosystem as we know

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##### <span style="color: #1f78b4"> Feb 25 FPGA </span>

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8:30	Keynote II: Xilinx’s Vitis Unified Software Platform (Chair: George Constantinides, Imperial College London)
Vinod Kathail (Xilinx)
9:00	Session: High-Level Abstractions and Tools II (Chair: Ilya Ganusov, Intel)
9:00	StateMover: Combining Simulation and Hardware Execution for Efficient FPGA Debugging
Sameh Attia(University of Toronto); Vaughn Betz(University of Toronto)
9:25	Buffer Placement and Sizing for High-Performance Dataflow Circuits
Lana Josipovic(École polytechnique fédérale de Lausanne); Shabnam Sheikhha(EPFL); Andrea Guerrieri(EPFL); Paolo Ienne(EPFL); Jordi Cortadella(Universitat Politecnica de Catalunya)
9:50	Closing Leaks: Routing Against Crosstalk Side-Channel Attacks
Zeinab Seifoori(Department of Computer Engineering, Sharif University of Technology (SUT)); Seyedeh Sharareh Mirzargar(EPFL); Mirjana Stojilovic(EPFL)
9:55	Built-in Self-Evaluation of First-Order Power Side-Channel Leakage for FPGAs
Ognjen Glamocanin(École Polytechnique Fédérale de Lausanne (EPFL)); Louis Coulon(École Polytechnique Fédérale de Lausanne (EPFL)); Francesco Regazzoni(ALaRI); Mirjana Stojilovic(EPFL)
10:00	Poster Session III (Chair: Kia Bazargan, University of Minnesota)
11:10	Session: Applications II (Chair: Grace Zgheib, Intel)
11:10	Dependency-Driven Trace-Based Network-on-Chip Emulation on FPGAs
Thiem V. Chu(Japan Advanced Institute of Science and Technology); Kenji Kise(Tokyo Institute of Technology); Kiyofumi Tanaka(Japan Advanced Institute of Science and Technology)
11:35	FPGA-Accelerated Samplesort For Large Data Sets
Han Chen(Stony Brook University); Sergey Madaminov(Stony Brook University); Michael Ferdman(Stony Brook University); Peter Milder(Stony Brook University)
12:00	BiS-KM: Enabling Any-Precision K-Means on FPGAs
Zhenhao He(ETH Zurich); Zeke Wang(ETH Zurich); Gustavo Alonso(ETH Zurich)
12:25	Flexible Communication Avoiding Matrix Multiplication on FPGA with High-Level Synthesis
Johannes de Fine Licht(ETH Zurich); Grzegorz Kwasniewski(ETH Zurich); Torsten Hoefler(ETH Zurich)
12:50	Lunch
14:10	Session: Deep Learning II (Chair: Lita Yang, Microsoft)
14:10	Accelerating GCN Training on CPU-FPGA Heterogeneous Platforms
Hanqing Zeng(University of Southern California); Viktor Prasanna(University of Southern California)
14:35	Reuse Kernels or Activations? A Flexible Dataflow for Low-latency Spectral CNN Acceleration
Yue Niu(University of Southern California); Rajgopal Kannan(USC); Ajitesh Srivastava(University of Southern California); Viktor K Prasanna(University of Southern California)
15:00	Coffee Break
16:00	Session: High-Level Synthesis and Tools (Chair: Peter Cheung, Imperial College London)
<span style="color: #e41a1c">16:00	Finding and Understanding Bugs in FPGA Synthesis Tools
Yann Herklotz(Imperial College London); John Wickerson(Imperial College London)
16:25	Combining Dynamic & Static Scheduling in High-level Synthesis
Jianyi Cheng(Imperial College London); Lana Josipovic(École polytechnique fédérale de Lausanne); George Constantinides(Imperial College London); Paolo Ienne(EPFL); John Wickerson(Imperial College London)</span>
16:50	Boyi: A Systematic Framework for Automatically Deciding the Best Execution Model for OpenCL Applications on FPGAs
Jiantong Jiang(Northeastern University); Xue Liu(Northeastern University); Juan Gómez-Luna(ETH Zurich); Nan Guan(The Hong Kong Polytechnic University); Qingxu Deng(Northeastern University); Wei Zhang(Hong Kong University of Science and Technology); Onur Mutlu(ETH Zurich and Carnegie Mellon University); Zeke Wang(ETH Zurich)
17:15	Conference closing- Best Paper Award

<span style="color: #e41a1c">1. Transpotation unbooked</span>
2. 【VKVNPTQ】RADISSON HOTEL SUNNYVALE - SILICON VALLEY, 1300 Chesapeake Terrace, Sunnyvale CA 94089

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## Silicon Valley

##### <span style="color: #1f78b4"> Feb 26 Silicon Valley </span>

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##### <span style="color: #1f78b4"> Feb 27 Silicon Valley </span>

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<span style="color: #e41a1c">1. Transpotation unbooked</span>
2. 【EKSWYG】VS41 SFO 17:00 to LHR 11:15 

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