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# System prepended metadata

title: 2025 年「資訊科技產業專案設計」作業 3

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# 2025 年「資訊科技產業專案設計」作業 3

> [**Resume**](https://www.canva.com/design/DAG5uX5s5WM/t3tuCytvNMK8fvguU6AruA/edit?utm_content=DAG5uX5s5WM&utm_campaign=designshare&utm_medium=link2&utm_source=sharebutton)
## 相關公司職務描述

### NVIDIA
:::spoiler
\
[**Senior Verification Engineer - Hardware**](https://nvidia.eightfold.ai/careers?start=0&pid=893392163264&sort_by=timestamp)
#### Job Description:

You will be responsible for creation of "state of the art" UVM based verification test benches and methodologies to verify complex IP's and Sub-systems. You will also get to work on System level verification using C/C++. During the course of a project you would end up driving the following aspects of verification for your unit:

- Architect the testbenches and craft verification environment using UVM methodology
- Define test plans, tests and verification infrastructure for modules, clusters and system
- Build efficient and reusable bus functional models, monitors, checkers and scoreboards
- Implement functional coverage and own verification closure
- Work with architects, designers, FPGA and post-silicon teams to ensure that your unit is robust

#### Requirement:

You should be BTech/MTech with 5+ years of experience in verification closure of complex Unit, Sub-system or SOC level verification. If you have experience in at least a few of the following domains, we will have an excellent match for our needs:

- CPU verification, Memory controller verification, Interconnect verification
- High Speed IO verification (UFS/PCIE/XUSB)
- 10G/1G Ethernet MAC and Switch
- Bus protocols (AXI/APB)
- System functions like Safety, Security, Virtualization and sensor processing
- Experience in the latest verification methodologies like UVM/VMM
- Exposure to industry standard verification tools for simulation and debug is a requiremen
- Exposure to Formal verification would be excellent
- Good debugging and analytical skills.
- Good interpersonal skills, ability to work as an excellent teammate with excellent communication skills to collaborate with cross-cultural teams and work in a matrix organization
:::

:::spoiler
\
[**ASIC Design Engineer - New College Grad 2026**](https://nvidia.eightfold.ai/careers?query=digital+design+engineer&start=0&pid=893391566289&sort_by=relevance&filter_job_type=new+college+graduate)
#### Job Description:

- As a key member of the GPU Design team, you will implement, document and deliver high performance, area and power efficient RTL to achieve design targets and specifications.
- Analyze architectural trade-offs based on features, performance requirements and system limitations.
- Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean design.
- Collaborate and coordinate with architects, other designers, pre- and post-silicon verification teams, synthesis, timing and back-end teams to accomplish your tasks.
- Work on a broad list of IPs such as GPU's work scheduler, time distribution system, interrupt controllers, and DMA engines.
- Architect features to help silicon debug and support post-silicon validation activities.

#### Requirement:

- Bachelors Degree or equivalent experience in Electrical Engineering, Computer Engineering or Computer Science.
- Experience in micro-architecture and RTL development (Verilog).
- Good understanding of ASIC design flow including RTL design, verification, logic synthesis and timing analysis.
- Exposure to Digital systems and VLSI design, Computer Architecture, Computer Arithmetic is required.
- Strong interpersonal skills and an excellent teammate.

#### Ways to stand out from the crowd:

- Strong C/C++, Python or Perl skills.
- Good debugging and analytical skills.
- Experience with arbiters, scheduling, synchronization & bus protocols, interconnect networks, caches 
:::

### Google
:::spoiler
\
[**Multimedia Digital Design Engineer, Silicon**](https://www.google.com/about/careers/applications/jobs/results/73094055768007366-multimedia-digital-design-engineer-silicon?skills=degital%20design%20engineer)
#### Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 4 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
- Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques.

#### Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science.
Experience with a scripting language like Perl or Python.
- Experience with Application-Specific Integrated Circuit (ASIC) or FPGA design verification, synthesis, timing/power analysis and Design for Testing (DFT).
- Knowledge of high performance and low power design techniques, assertion-based formal verification, FPGA and emulation platforms and SOC architecture.
- Knowledge of memory compression, fabric, coherence, cache, or Dynamic Random Access Memory (DRAM).

#### Job Description
- Define the block level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.).
- Perform RTL coding, function/performance simulation debug, and Lint/CDC/FV/UPF checks.
- Participate in synthesis, timing/power closure, and Field-programmable Gate Array (FPGA)/silicon bring-up.
- Participate in test plan and coverage analysis of the block and ASIC-level verification.
Communicate and work with multi-disciplined and multi-site teams.
:::

:::spoiler
\
[**Design Verification Engineer, CPU, Google Cloud**](https://www.google.com/about/careers/applications/jobs/results/130274548409868998-design-verification-engineer-cpu-google-cloud?skills=digital%20verification)


#### Minimum qualifications:
- Bachelor's degree in Electrical Engineering or equivalent practical experience.
3 years of experience verifying digital logic at RTL level using SystemVerilog, or Specman/E for FPGAs or ASICs.
- Experience creating and using verification components and environments in standard verification methodology.
- Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems).

#### Preferred qualifications:
- Master’s degree in Electrical Engineering, Computer Science, or a related field.
- Experience with UVM, SystemVerilog, or other scripting languages (e.g., Python, Perl, Shell, Bash, etc.).
- Experience with CPU implementation, assembly language, or compute System on a Chip (SOC).

#### Job Description
- Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
- Create and enhance constrained-random verification environments using SystemVerilog/UVM, or Specman.
- Identify and write all types of coverage measures for stimulus and corner-cases.
- Debug tests with design engineers to deliver functionally correct design blocks.
- Lead coverage measures to identify verification holes and to show progress towards tape-out.
:::

### RealTek

:::spoiler
\
[**微處理器設計工程師**](https://recruit.realtek.com/Job/JobDetail?jobid=716)
#### Job Description：微處理器設計工程師(Processor Design Engineer)

#### Requirement：
- 碩士以上電機資訊相關科系畢
- 熟悉 Verilog RTL 及 Synthesis, Simulation 等相關 IC Design Flow
- 熟悉 Computer Architecture
- 有下列經驗者更佳：
(1)Microprocessor或DSP相關硬體設計
(2)On-chip Bus, DDR/Flash Memory Controller, PCIE, USB等設計
:::

:::spoiler
\
[**CPU數位IC設計工程師**](https://recruit.realtek.com/Job/JobDetail?jobid=1478)
#### Job Description：
Microprocessor design. Desired skills and experience includes:
1. Knowledge of DSP, microprocessor and computer architecture fundamentals.
2. Experience in RTL design and ability to make trade-offs between power, performance and area appropriately.
3. Experience in the microprocessor design cycle: initial concept, micro-architecture, implementation, verification, documentation and support.

#### Requirement：
1. 碩士以上; 電子、電機、資工、電信、電控、資科等相關科系畢業為主。
2. 具相關工作經驗者尤佳。
:::

### MediaTek

:::spoiler
\
[**Digital IC designer**](https://careers.mediatek.com/eREC/JobSearch/JobDetail/MTK120191111002?returnUrl=%2FeREC%2FJobSearch%3FsortBy%3D%26order%3D%26page%3D1%26searchKey%3Ddigital%2520design%26category%3D%26workExp%3D%26branch%3D%26program%3D)

#### Job Description：
- Digital design (RTL design, Synthesis, integration, verification)
- SoC Chip design, integration
- Familiar with VLSI design flow is a plus
#### Requirement :
- Majored in electrical and electronics and Computer Science
- Experience in VLSI courses is a plus
:::

:::spoiler
\
[**Neural Processing Unit Digital Designer**](https://careers.mediatek.com/eREC/JobSearch/JobDetail/MTK120240821014?returnUrl=%2FeREC%2FJobSearch%3FsortBy%3D%26order%3D%26page%3D2%26searchKey%3Ddigital%2520design%26category%3D%26workExp%3D%26branch%3D%26program%3D)
#### Job Description：
Mediatek Neural/AI Processing Unit (NPU/APU) enables AI applications in all Mediatek's products, such as smartphones, tablets, TVs, smart-cameras, and automobiles. It has been recognized as the NPU with worldwide leading PPA for edge devices.
As a NPU digital hardware designer, you will join the APU IP development procedures, including architecture, u-architecture, RTL, verification, and PPA optimization. Join us, and you will enjoy your contribution to ubiquitous AI.

#### Requirement :
- Familiar with Verilog design
- Familiar with digital design flow, such as synthesis, STA, power analysis
- Familiar with at least one of following tasks
    - AI processing unit design
    - Paralleling processing design
    - DSP/processor design
    - Arithmetic operation designs
    - Bus interface or fabric design, especially AMBA
    - Design integration
:::
## 自己在專業上匹配的程度

### 職缺分析
- Digital Design Engineer (DD)
    - 電機工程、電信工程、電控工程、資訊工程相關科系碩士畢業。
    - 除了基本的 RTL 能力外，要熟悉 ic design flow、timing analysis、low-power design techniques。
    - 熟悉 Computer Architecture (除了CPU外，其他硬體如 DDR、AXI 等也要有一定程度的了解)
    - 有過開發 **MCU**、DSP design、**DDR/Flash Memory Controller**  等硬體設計經驗。
    - **影像處理，影像壓縮**。
    - 參與過 data bus access/arbitration相關控制電路設計。
    - 有修過相關課程，如 VLSI、Computer Architecture等。
    - 熟悉如何優化 PPA (Power、Performance、Area)
    - C、C++、Python、Perl
    - 看重 debug 跟分析問題的能力。
    - 除了個人能力，也看重團隊溝通能力。
- Digital Verification Engineer (DV)
    - 電機工程、電信工程、電控工程、資訊工程相關科系碩士畢業。
    - 熟悉 RTL(System Verilog) 跟 UVM
    - 熟悉 SOC 組成 (如CPU、Memory、Bus、Interconnect等)
    - 有 Verification 的相關經驗
    - 解決問題的能力 (Debugging、Analytical)
    - 團隊溝通能力

### 與職缺所需符合程度
- 大學 CS，碩班 EE
- 熟悉 RTL，並有實作大型專案的經驗
- 有跑過 IC design flow，包含 synthesize, APR
- 修過 Advanced VLSI System Design、Computer Architecture等相關課程，並有相關開發經驗 (SoC)
- 在職缺中列出的實務經驗中，有實做過 CPU / AI Processing Unit、Arithmetic Units、AXI Bus、Memory hierarchy (Cache、DRAM)
- 基本程式語言能力 C、C++、Python
### 缺乏之處
- Google、Nvidia 看重英文，我的英語對話能力欠佳
- 實驗室不是 IC 相關的
- 雖然有跑過完整的 IC Design Flow，但不太熟悉如何使用 GUI 介面或是寫 Script
- 缺乏 DSP 的實作經驗 (看很多職缺都有要求)
- 缺乏驗證的相關經驗
- 目前沒有 Low Power Design 的相關經驗
- 欠缺一些 IC 的 knowledge
## 面試題目

- CDC
    - Metastability
    - Two flip-flop synchronizer
    - Pulse synchronizer
    - Mux synchronizer
    - Async FIFO
    - 為甚麼多bit數據傳輸, 不能使用1-bit synchronizer分別同步
    - two flip-flop synchronizer / three flip-flop synchronizer差別
- SDC
    - False path
    - multi cycle (為何合成時 Constraint 要這樣下)
    - input / output delay
    - max / min delay
- Timing
    - Setup / Hold time 的解釋或計算
    - hold time 可以是 0 嗎
    - Violation 怎麼解決
    - 什麼是STA，如何找 critical path
    - STA timing report 的內容
    - STA vs DTA
- IC Design Flow
    - Synthesize、APR
    - 合成時 Clock 的頻率取決於哪些因素
    - 合成需要哪些檔案
    - APR 如何做 timing optimization
    - Pre / Post Sim 差異
- Difference
    - Synchronous vs Asynchronous reset
    - Blocking vs Non-Blocking
    - Latch vs Flip-flop
    - FSM : Mealy vs Moore
- Clock Skew
- 用 NAND 拼出 OR (很多類似的題目 : 用 ? 組出 ?)
- Clock Gating (設計電路以及優缺點)
- Counter (同步、非同步、反向)
- 除頻電路 (Verilog : 設計除N電路)
- AXI protocol
- 給 Waveform 寫 RTL
- 舉幾個 low power methodology
- Glitch
## 模擬面試
> 🙋‍ : interviewee
> 👨‍💻 : interviewer
### 背景知識 : 
👨‍💻 : 請解釋 setup time, hold time

🙋‍ : Setup time 是資料在時脈上升或下降之前，保持穩定的最小時間，也就說資料要提早到來，以免採樣到錯誤的資料。Hold time 是資料在時脈觸發上升或下降之後，必須保持穩定不能改變的最小時間，也就說資料不能太快改變，不然也會採樣到錯誤的資料。

👨‍💻 : 那為什麼要滿足 Setup 跟 Hold time?

🙋‍ : 剛剛有提到，在 clock edge 前資料必須有足夠的時間被採樣。若是資料太晚到來，就會違反 setup，會導致 flip flop 抓到錯誤的資料，可能讓整個晶片無法正常的運作，那 Hold time 也是相同的意思。

👨‍💻 : 若發生setup time & hold time violation分別該怎麼處理

🙋‍ : 在電路的邏輯太複雜或是 clock 頻率太快，就會發生 setup time violation，那最簡單的方式就是降低 clock frequency，不然就是減少資料路徑延遲，像是 pipeline。那當資料太快到下一個 flip flop，就會發生 hold time violation，可以增加一些 buffer 來讓資料延遲。

👨‍💻 : 請解釋亞穩態

🙋‍ : 當 setup / hold time violation 時，訊號會呈現一個不是 0 也不是 1 的狀態。

👨‍💻 : 在 CDC 中如何避免亞穩態?

🙋‍ : 在多個單元用的時脈不同的情況下，也就是 CDC 的問題，就可能會發生亞穩態。那解決方式要看資料的位元數來決定。如果是單個位元，可以使用兩級的 flip flop 來避免，第一級可能進入亞穩態，但第二級有足夠的時間解析成穩定值。那如果是多個位元，可以使用 Asynchronous FIFO

👨‍💻 : 低頻率的clock傳輸數據到高頻率的clock, 造成高頻率的clock多次重覆取到data, 你會如何解決?

🙋‍ : 可以用一個握手機制，低頻送資料，高頻收到後回 ACK，低頻才更新資料，能確保資料只被高頻端接受一次，不會重複讀取。

## Reference
https://www.ptt.cc/bbs/Tech_Job/M.1472189407.A.993.html
https://hackmd.io/@mY6ukBHKSIG5P_4sveSdtA/HJ50IHfri#ICD-Knowledge
https://www.dcard.tw/f/tech_job/p/240953224
https://www.ptt.cc/bbs/Tech_Job/M.1641268306.A.9FF.html
