# [SOC] Lab03
## Introduction
This Lab 3 primarily designs a FIR filter to implement the following function.

> y[n]=Σ(h[i]∗x[n-i])


Additionally, since the input and output data need to communicate with external components, such as memory, we need to use AXI-LITE and AXI-Stream as interfaces.

#### Design specification
* data_width: 32 bit
* tap_width: 32 bit
* data_Num: TBD –Based on the size of the data file
* tap_number: up to 32
:::warning
* Only one Multiplier and one Adder can be used.
* Shift registers and Tap coefficient should be implemented with SRAM
:::

#### Configuration Register Address map
* addr 0x00: [2] ap_idle, [1] ap_done, [0] ap_start
* addr 0x10: data-length
* addr 0x14: number of taps (Max: 32)
* addr 0x80 ~ 0xFF: Tap parameters

## Block Diagram
### Datapath – dataflow

### Control signals

## Describe the operation, e.g.
##### How to receive data-in and tap parameters and place into SRAM
##### How to access DataRAM and tapRAM to do the computation
### How `ap_done` is generated.
### 

## Resource usage
### Including FF, LUT, BRAM

### Area

## Performance report
### Latency & throughput (# of clocks to generate a Y output)

## Timing Report
### Synthesize the design with a maximum frequency
### Report timing on the longest path, slack

## Simulation Waveform, show
### Coefficient program, and read back
#### read back

### Data-in stream-in

### Data-out stream-out

### RAM access control