# [SOC] Week10 Question

:::info
:bulb:there are 5 question in this week .
:::

## Q1:Calculate cache size and tag addresses

### Ans:
#### The total cache size = 64B * 4K = 256KB
#### The address range in the tag:
1.Assume memory address is 32-bit
2.Number of sets = 4K / 4 = 1K => index bits = log2(1024) = 10bits
3.Cache size = 64B => offset bits = log2(64) = 6bits

=> 32 - 10 - 6 = 16bits

## Q2:MESI protocol exercise
### Ans:
# MESI Protocol Exercise Solution

Here's the completed table for the MESI protocol exercise:

| Operation | P1$ | P2$ | P3$ | P4$ | Memory | Bus Operation | Which supply data |
|----------------------|-----|-----|-----|-----|--------|-------------------------|-------------------|
| Initial State a X | I | I | I | I | 0 | - | - |
| P1 load X | E | I | I | I | 0 | Read | Memory |
| P2 load X | S | S | I | I | 0 | Read | Memory |
| P1 store X (1) | M | I | I | I | 0 | Read-Exclusive | P1$ |
| P3 load X | S | I | S | I | 1 | Read | P1$ |
| P3 store X (2) | I | I | M | I | 1 | Read-Exclusive-Invalidate | P3$ |
| P2 load X | I | S | S | I | 2 | Read | P3$ |
| P1 load X | S | S | S | I | 2 | Read | P3$ |

## Q3:memory system performance improvement techniques
### Ans:
| Design Techniques | Category (A, B, C) |
|--------------------------------------------------|--------------------|
| Reduce memory access latency | A |
| Higher cache associativity | B |
| Processor multithreading, OoO execution | C |
| Bigger cache | B |
| Virtually indexed physically tagged Cache (VIPT Cache) | A |
| Prefetch | B |
| Non-blocking caches | C |
| Critical word first | C |
| Read bypass write | A |

## Q4:MESI protocol exercise
### Ans:
A( Row-major order) is better. Due to spatial locality.

## Q5:MESI protocol exercise
### Ans:

#### How many memory channels?
1-bit=> 2 channels
#### How many DIMMs are in each channel?
1-bit=> 2 DIMMs in each channel
#### How many banks are in each DIMM?
3-bit(bamk)+1-bit(Rank) => 16banks in each DIMM

#### If we have a dataset of 256B sequentially accessed, which CPU address bit should be assigned for channel decoding?
log2(256)=8 => bit 8 (address[8])