---
# System prepended metadata

title: Sequential CPU

---

Sequential CPU
===

Wednesday 11 am ~ 4:30 pm
Thursday 11 am ~ 8 pm, except 3:30~4:15
Friday 11 am ~ 8pm

an ALU, a control unit, a system memory, registers


https://www.fpga4student.com/2017/04/verilog-code-for-16-bit-risc-processor.html


https://stanford.edu/~sebell/oc_projects/ic_design_finalreport.pdf

Test Case 1 NOP (based on JMPing to next PC)
---
```
`timescale 1ns/1ps

module test1_nop(
   input [7:0] Read_Address,
	output [7:0] instruction,
	output [6:0] digit1,
	output [6:0] digit2
);

	wire [7:0] MemByte[31:0];
   bcd    s2_(Read_Address[7:4], digit2);
   bcd    s1_(Read_Address[3:0], digit1);
	assign MemByte[0] = {2'b11,  2'b00, 2'b00, 2'b00};

	assign MemByte[1] = {2'b11,  2'b00, 2'b00, 2'b00};

	assign MemByte[2] = {2'b11,  2'b00, 2'b00, 2'b00};

	assign MemByte[3] = {2'b11,  2'b00, 2'b00, 2'b00};

	assign MemByte[4] = {2'b11,  2'b00, 2'b00, 2'b10};

	assign instruction = MemByte[Read_Address];

endmodule
```

Test Case 2
---



