# `fpga-toolchain`

digraph {
"Verilog (.v)" [shape=note]
"SystemVerilog (.sv)" [shape=note]
"VHDL (.vhdl, .vhd)" [shape=note]

yosys [shape=box]
"Verilog (.v)" -> yosys  [label="2005, etc."]
"SystemVerilog (.sv)" -> yosys  [label="subset only"]
yosys -> "RTLIL (.il)"  [label="write_rtlil"]
yosys -> "JSON (.json)"  [label="json"]
yosys -> "dot"  [label="show -format dot"]

"JSON (.json)"
"RTLIL (.il)"
"VCD"
"FST"
"dot"

GTKWave [shape=box]
verilator [shape=box]
XDot [shape=box]
"dot" -> XDot
}