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fpga-toolchain







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Verilog (.v)



Verilog (.v)



yosys

yosys



Verilog (.v)->yosys


2005, etc.



SystemVerilog (.sv)



SystemVerilog (.sv)



SystemVerilog (.sv)->yosys


subset only



VHDL (.vhdl, .vhd)



VHDL (.vhdl, .vhd)



RTLIL (.il)

RTLIL (.il)



yosys->RTLIL (.il)


write_rtlil



JSON (.json)

JSON (.json)



yosys->JSON (.json)


json



dot

dot



yosys->dot


show -format dot



XDot

XDot



dot->XDot





VCD

VCD



FST

FST



GTKWave

GTKWave



verilator

verilator
Last changed by 
 
hkienle
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Schoko-Hafer Kekse nach Britt

vegan und glutenfrei

May 15, 2025
Einreichung: Einkaufstrolley (OSH-Prototyp)

Einreichung zu KONSTRUKTIV!: Der Open Hardware Wettbewerb

Apr 30, 2025
7 Augenpaare

IMG_20210831_143504

Apr 29, 2025
`diy-gridbeam` Gridbeam building system

system holes: 2, 3, 4, 5, 6, 8, ...![](https://i.imgur.com/pV2fdtW.png =200x) wood and aluminum are interchangeable (but different hole diameters)![](https://i.imgur.com/pUssNQV.png =200x) count holes to duplicate structures![](https://i.imgur.com/mlEQZVy.png =200x) custom parts with matching grid pattern![](https://i.imgur.com/NDbM6Wa.jpg =200x) tri-joint![](https://i.imgur.com/2fi1N2Y.png =200x) ![](https://i.imgur.com/ARfFYRx.png =200x) ![](https://i.imgur.com/mfkvYUj.png =200x) tri-joint with double-beam (unoffical?)![](https://i.imgur.com/Gvo4SjT.png =200x) (all axes could be doubled, also note "spare" hole pattern)![](https://i.imgur.com/ot1pxhL.png =200x) :link: ![](https://i.imgur.com/qXrgDjA.png =x200) :link: minimum/sparse hole patterns (abandoned)![](https://i.imgur.com/l08fR0D.png =300x) panels (plywood) as structural element replacing beams :link:![](https://i.imgur.com/PtdJhzt.png =x200) panels have 12mm thickness

Feb 19, 2025
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Published on HackMD