# VGA Display Minesweeper Game
A 10x10 minesweeper game written by verilog
[Toc]
## Architecture
## Top Module
```verilog=
module mine_game(
input clk,
input rst,
/* Keyboard input */
input ps2_clk,
input ps2_data,
/* VGA display */
output hsync,
output vsync,
output [3:0] red,
output [3:0] green,
output [3:0] blue,
/* Seven segment display */
output [6:0] hundreds,
output [6:0] tens,
output [6:0] units,
/* Dot matrix display */
output [7:0] dot_row,
output [7:0] dot_col
);
/* VGA Clock */
wire clk_25M;
/* Matrix Clock */
wire clk_matrix;
/* Timer Clock */
wire clk_1;
/*
pointer_x: A unsigned integer indicate the pointer's x position
pointer_y: A unsigned integer indicate the pointer's y position
click: 1 bit contain button status.
*/
wire [3:0] pointer_x;
wire [3:0] pointer_y;
wire click;
/*
game_map: This variable contains 10x10 blocks' current status.
|empty|open|bomb|n[2]|n[1]|n[0]|
block_position: Passing the index of map
block_data: Return the map data in 'block_position' index.
game_over: 1 for game_over
*/
wire [6:0] block_position;
wire [5:0] block_data;
wire game_over;
clk_div #(0) u0(clk, clk_25M);
clk_div #(16667) u1(clk, clk_matrix);
clk_div #(25000000) u2(clk, clk_1);
keyboard_driver (ps2_clk, ps2_data, rst, pointer_x, pointer_y, click);
seven_driver (clk_1, rst, game_over, hundreds, tens, units);
mine_logic (rst, pointer_x, pointer_y, click, block_position, block_data, game_over);
vga_driver (clk_25M, rst, pointer_x, pointer_y, block_position, block_data, hsync, vsync, red, green, blue);
matrix_driver (clk_matrix, rst, game_over, dot_row, dot_col);
endmodule
```
## Clock divider
```verilog=
module clk_div #(parameter div = 0) (
input clk,
output reg clk_out
);
reg [31:0] counter;
always @(posedge clk) begin
if (counter == div) begin
clk_out <= ~clk_out;
counter <= 0;
end else begin
counter <= counter + 1;
end
end
endmodule
```
## PS/2 Keyboard
接入 PS/2 鍵盤，在上下左右與空白被按下時計算現在位置並輸出 x y position 與 click
```verilog=
module keyboard_driver(
input clk,
input data,
input rst,
output [3:0] ox,
output [3:0] oy,
output reg click
);
reg [4:0] byte_count;
reg [7:0] keycode;
reg [4:0] x;
reg [4:0] y;
reg complete;
assign ox = x >> 2;
assign oy = y >> 2;
always @(posedge clk or negedge rst) begin
if (~rst) begin
byte_count <= 0;
x <= 0;
y <= 0;
click <= 0;
complete <= 0;
end else begin
if (byte_count <= 10)
byte_count <= byte_count + 1;
else
byte_count <= 0;
if (byte_count == 0)
keycode <= 0;
else if (byte_count == 1)
keycode[0] <= data;
else if (byte_count == 2)
keycode[1] <= data;
else if (byte_count == 3)
keycode[2] <= data;
else if (byte_count == 4)
keycode[3] <= data;
else if (byte_count == 5)
keycode[4] <= data;
else if (byte_count == 6)
keycode[5] <= data;
else if (byte_count == 7)
keycode[6] <= data;
else if (byte_count == 8)
keycode[7] <= data;
else if (byte_count == 9)
complete <= 1;
else begin
complete <= 0;
keycode <= 0;
byte_count <= 0;
click <= 0;
end
if (complete && keycode == 8'd41) begin
click <= 1;
end else if (complete && keycode == 8'd117) begin
if (y == 0) y <= 0; else y <= y - 1;
end else if (complete && keycode == 8'd114) begin
if (y == 18) y <= 18; else y <= y + 1;
end else if (complete && keycode == 8'd107) begin
if (x == 0) x <= 0; else x <= x - 1;
end else if (complete && keycode == 8'd116) begin
if (x == 18) x <= 18; else x <= x + 1;
end else begin
x <= x;
y <= y;
end
end
end
endmodule
```
## Mouse Driver (deprecated)
```verilog=
module mouse_driver(
input clk,
input rst,
input data,
output reg [9:0] x,
output reg [9:0] y,
output reg click
);
/* Internal buffer for data recevicing */
reg complete;
reg [4:0] byte_count;
reg x_ov;
reg y_ov;
reg internal_click;
reg signed [8:0] internal_x;
reg signed [8:0] internal_y;
always @(negedge clk or negedge rst) begin
if (~rst) begin
byte_count <= 0;
end else begin
if (byte_count == 0)
y_ov <= data;
else if (byte_count == 1)
x_ov <= data;
else if (byte_count == 2)
internal_y[8] <= data;
else if (byte_count == 3)
internal_x[8] <= data;
else if (byte_count == 6)
internal_click <= data;
else if (byte_count == 8)
internal_x[7] <= data;
else if (byte_count == 9)
internal_x[6] <= data;
else if (byte_count == 10)
internal_x[5] <= data;
else if (byte_count == 11)
internal_x[4] <= data;
else if (byte_count == 12)
internal_x[3] <= data;
else if (byte_count == 13)
internal_x[2] <= data;
else if (byte_count == 14)
internal_x[1] <= data;
else if (byte_count == 15)
internal_x[0] <= data;
else if (byte_count == 16)
internal_y[7] <= data;
else if (byte_count == 17)
internal_y[6] <= data;
else if (byte_count == 18)
internal_y[5] <= data;
else if (byte_count == 19)
internal_y[4] <= data;
else if (byte_count == 20)
internal_y[3] <= data;
else if (byte_count == 21)
internal_y[2] <= data;
else if (byte_count == 22)
internal_y[1] <= data;
else
internal_y[0] <= data;
if (byte_count == 23) begin
byte_count <= 0;
complete <= 1;
end else begin
byte_count <= byte_count + 1;
complete <= 0;
end
end
end
always @(posedge complete) begin
if (x_ov) begin
if (x <= 255 && internal_x[8] == 1) begin
x <= 0;
end else if (x + 255 >= 639 && internal_x[8] == 0) begin
x <= 639;
end else if (internal_x[8] == 1) begin
x <= x - 255;
end else begin
x <= x + 255;
end
end else begin
if (internal_x < 0 && x < -internal_x) begin
x <= 0;
end else if (internal_x > 0 && x + internal_x >= 639) begin
x <= 639;
end else begin
x <= x + internal_x;
end
end
if (y_ov) begin
if (y <= 255 && internal_y[8] == 1) begin
y <= 0;
end else if (y + 255 >= 479 && internal_y[8] == 0) begin
y <= 479;
end else if (internal_x[8] == 1) begin
y <= y - 255;
end else begin
y <= y + 255;
end
end else begin
if (internal_y < 0 && y < -internal_y) begin
y <= 0;
end else if (internal_y > 0 && y + internal_y >= 479) begin
y <= 479;
end else begin
y <= y + internal_y;
end
end
end
endmodule
```
## Keypad (deprecated)
```verilog=
module keypad_driver(
input keypadcol,
input click_i,//button
input rst,
output reg [3:0]keypadrow,
output reg [9:0] x,
output reg [9:0] y,
output reg click_o
);
always @(negedge rst) begin
if (~rst) begin
x <= 0;
y <= 0;
click_o <= 0;
end else begin
case(keypadcol) begin
4'b0111 : x <= x - 1;
4'b1011 : y <= y - 1;
4'b1101 : y <= y + 1;
4'b1110 : x <= x + 1;
end
case(click_i) begin
0 : click_o <= 0;
1 : click_o <= 1;
end
end
end
endmodule
```
## Mine Logic
click 訊號 Posedge 時使用 x y 值來打開方塊
內部需要有一個 game_over flag，按到炸彈時寫為 1 同時停止處理滑鼠點擊
地圖（Python）：
```
[.1 .1 11 -1 -1 21 .2 .2 .2 .2]
[11 11 12 2 2 21 21 .2 .2 .2]
[ 2 -1 3 1 2 -1 21 .2 .2 .2]
[ 3 -1 3 -1 2 1 21 21 21 21]
[-1 3 32 31 32 1 1 1 -1 1]
[-1 3 31 .3 31 -1 31 31 31 31]
[ 3 -1 31 .3 31 31 31 .3 .3 .3]
[-1 3 31 .3 .3 .3 .3 .3 .3 .3]
[-1 3 31 .3 .3 .3 .3 .3 .3 .3]
[ 2 -1 31 .3 .3 .3 .3 .3 .3 .3]
```
地圖（Verilog）:
```verilog!
map[0] <= 8'b01100001;
map[1] <= 8'b01100001;
map[2] <= 8'b01000001;
map[3] <= 8'b00001000;
map[4] <= 8'b00001000;
map[5] <= 8'b10000001;
map[6] <= 8'b10100010;
map[7] <= 8'b10100010;
map[8] <= 8'b10100010;
map[9] <= 8'b10100010;
map[10] <= 8'b01000001;
map[11] <= 8'b01000001;
map[12] <= 8'b01000010;
map[13] <= 8'b00000010;
map[14] <= 8'b00000010;
map[15] <= 8'b10000001;
map[16] <= 8'b10000001;
map[17] <= 8'b10100010;
map[18] <= 8'b10100010;
map[19] <= 8'b10100010;
map[20] <= 8'b00000010;
map[21] <= 8'b00001000;
map[22] <= 8'b00000011;
map[23] <= 8'b00000001;
map[24] <= 8'b00000010;
map[25] <= 8'b00001000;
map[26] <= 8'b10000001;
map[27] <= 8'b10100010;
map[28] <= 8'b10100010;
map[29] <= 8'b10100010;
map[30] <= 8'b00000011;
map[31] <= 8'b00001000;
map[32] <= 8'b00000011;
map[33] <= 8'b00001000;
map[34] <= 8'b00000010;
map[35] <= 8'b00000001;
map[36] <= 8'b10000001;
map[37] <= 8'b10000001;
map[38] <= 8'b10000001;
map[39] <= 8'b10000001;
map[40] <= 8'b00001000;
map[41] <= 8'b00000011;
map[42] <= 8'b11000010;
map[43] <= 8'b11000001;
map[44] <= 8'b11000010;
map[45] <= 8'b00000001;
map[46] <= 8'b00000001;
map[47] <= 8'b00000001;
map[48] <= 8'b00001000;
map[49] <= 8'b00000001;
map[50] <= 8'b00001000;
map[51] <= 8'b00000011;
map[52] <= 8'b11000001;
map[53] <= 8'b11100011;
map[54] <= 8'b11000001;
map[55] <= 8'b00001000;
map[56] <= 8'b11000001;
map[57] <= 8'b11000001;
map[58] <= 8'b11000001;
map[59] <= 8'b11000001;
map[60] <= 8'b00000011;
map[61] <= 8'b00001000;
map[62] <= 8'b11000001;
map[63] <= 8'b11100011;
map[64] <= 8'b11000001;
map[65] <= 8'b11000001;
map[66] <= 8'b11000001;
map[67] <= 8'b11100011;
map[68] <= 8'b11100011;
map[69] <= 8'b11100011;
map[70] <= 8'b00001000;
map[71] <= 8'b00000011;
map[72] <= 8'b11000001;
map[73] <= 8'b11100011;
map[74] <= 8'b11100011;
map[75] <= 8'b11100011;
map[76] <= 8'b11100011;
map[77] <= 8'b11100011;
map[78] <= 8'b11100011;
map[79] <= 8'b11100011;
map[80] <= 8'b00001000;
map[81] <= 8'b00000011;
map[82] <= 8'b11000001;
map[83] <= 8'b11100011;
map[84] <= 8'b11100011;
map[85] <= 8'b11100011;
map[86] <= 8'b11100011;
map[87] <= 8'b11100011;
map[88] <= 8'b11100011;
map[89] <= 8'b11100011;
map[90] <= 8'b00000010;
map[91] <= 8'b00001000;
map[92] <= 8'b11000001;
map[93] <= 8'b11100011;
map[94] <= 8'b11100011;
map[95] <= 8'b11100011;
map[96] <= 8'b11100011;
map[97] <= 8'b11100011;
map[98] <= 8'b11100011;
map[99] <= 8'b11100011;
```
```verilog=
module mine_logic(
input rst,
input [3:0] position_x,
input [3:0] position_y,
input click,
/* |empty|open|bomb|n[2]|n[1]|n[0]| */
input [6:0] block_position,
output [5:0] block_data,
output reg game_over
);
reg [5:0] map[0:99];
reg [7:0] i;
wire [6:0] position;
wire [5:0] click_block;
wire [6:0] adj_0;
wire [6:0] adj_1;
wire [6:0] adj_2;
wire [6:0] adj_3;
wire [6:0] adj_5;
wire [6:0] adj_6;
wire [6:0] adj_7;
wire [6:0] adj_8;
assign block_data = map[block_position];
assign position = position_y * 10 + position_x;
assign click_block = map[position];
/*
| adj_0 | adj_1 | adj_2 |
| adj_3 | block | adj_5 |
| adj_6 | adj_7 | adj_8 |
*/
assign adj_0 = (position_y >= 1 ? position_y - 1 : 0) * 10 + (position_x >= 1 ? position_x - 1 : 0);
assign adj_1 = (position_y >= 1 ? position_y - 1 : 0) * 10 + position_x;
assign adj_2 = (position_y >= 1 ? position_y - 1 : 0) * 10 + (position_x <= 8 ? position_x + 1 : 9);
assign adj_3 = position_y * 10 + (position_x >= 1 ? position_x - 1 : 0);
assign adj_5 = position_y * 10 + (position_x <= 8 ? position_x + 1 : 9);
assign adj_6 = (position_y <= 8 ? position_y + 1 : 9) * 10 + (position_x >= 1 ? position_x - 1 : 0);
assign adj_7 = (position_y <= 8 ? position_y + 1 : 9) * 10 + position_x;
assign adj_8 = (position_y <= 8 ? position_y + 1 : 9) * 10 + (position_x <= 8 ? position_x + 1 : 9);
always @(posedge click or negedge rst) begin
if (~rst) begin
game_over <= 0;
end else begin
// click and judge is open
// block is not empty and block is not bomb
if((click_block & 6'b101000) == 6'b000000) begin
map[position] <= map[position] | 6'b010000; // open this block
// block is empty
end else if ((click_block & 6'b100000) == 6'b100000) begin
for (i = 0; i < 100; i = i + 1) begin
if (
// block is empty and adjacent to click_block
((map[i] & 6'b100000) == 6'b100000 && (map[i] & 3'b111) == (click_block & 3'b111)) ||
// block is not empty but adjacent to click_block
(map[i] & 6'b101000) == 6'b000000 && (
(map[adj_0] & 6'b101111) == (map[i] & 6'b101111) ||
(map[adj_1] & 6'b101111) == (map[i] & 6'b101111) ||
(map[adj_2] & 6'b101111) == (map[i] & 6'b101111) ||
(map[adj_3] & 6'b101111) == (map[i] & 6'b101111) ||
(map[adj_5] & 6'b101111) == (map[i] & 6'b101111) ||
(map[adj_6] & 6'b101111) == (map[i] & 6'b101111) ||
(map[adj_7] & 6'b101111) == (map[i] & 6'b101111) ||
(map[adj_8] & 6'b101111) == (map[i] & 6'b101111)
)
) begin
map[i] <= map[i] | 6'b010000;
end else begin
// do nothing
map[i] <= map[i];
end
end
// block is bomb
end else if ((click_block & 6'b001000) == 6'b001000) begin
game_over <= 1;
end
end
end
endmodule
```
## Seven Display
```verilog=
module seven_driver(
input clk,
input rst,
input game_over,
output [6:0] hundreds,
output [6:0] tens,
output [6:0] units
);
reg [9:0] count;
wire [3:0] display_100;
wire [3:0] display_10;
wire [3:0] display_1;
assign display_100 = (count / 100) % 10;
assign display_10 = (count / 10) % 10;
assign display_1 = count % 10;
seven_display(display_100, hundreds);
seven_display(display_10, tens);
seven_display(display_1, units);
always @(posedge clk or negedge rst) begin
if(~rst) begin
count <= 0;
end else begin
if (game_over) begin
count <= count;
end else begin
count <= count + 1;
end
end
end
endmodule
module seven_display(
input [3:0] value,
output reg [6:0] out
);
always @(value) begin
case(value)
0: out <= 7'b1000000;
1: out <= 7'b1111001;
2: out <= 7'b0100100;
3: out <= 7'b0110000;
4: out <= 7'b0011001;
5: out <= 7'b0010010;
6: out <= 7'b0000010;
7: out <= 7'b1111000;
8: out <= 7'b0000000;
9: out <= 7'b0010000;
10: out <= 7'b0001000;
11: out <= 7'b0000011;
12: out <= 7'b1000110;
13: out <= 7'b0100001;
14: out <= 7'b0000110;
15: out <= 7'b0001110;
endcase
end
endmodule
```
## Matrix Display
```verilog=
module matrix_driver(
input clk,
input rst,
input game_over,
output reg [7:0] dot_row,
output reg [7:0] dot_col
);
reg [2:0] row_count;
always @(posedge clk or negedge rst) begin
if(~rst) begin
dot_row <= 8'b11111111;
dot_col <= 8'b00000000;
row_count <= 3'd0;
end else begin
row_count <= row_count + 1;
case (row_count)
3'd0 : dot_row <= 8'b01111111;
3'd1 : dot_row <= 8'b10111111;
3'd2 : dot_row <= 8'b11011111;
3'd3 : dot_row <= 8'b11101111;
3'd4 : dot_row <= 8'b11110111;
3'd5 : dot_row <= 8'b11111011;
3'd6 : dot_row <= 8'b11111101;
3'd7 : dot_row <= 8'b11111110;
endcase
if (~game_over) begin
row_count <= 8'b00000000;
end else begin
case (row_count)
3'd0 : dot_col <= 8'b10000001;
3'd1 : dot_col <= 8'b01000010;
3'd2 : dot_col <= 8'b00100100;
3'd3 : dot_col <= 8'b00011000;
3'd4 : dot_col <= 8'b00011000;
3'd5 : dot_col <= 8'b00100100;
3'd6 : dot_col <= 8'b01000010;
3'd7 : dot_col <= 8'b10000001;
endcase
end
end
end
endmodule
```
## VGA Display
```verilog=
module vga_driver(
input clk,
input rst,
input [3:0] x,
input [3:0] y,
input [5:0] block_data,
output [9:0] block_position,
output hsync,
output vsync,
output [3:0] red,
output [3:0] green,
output [3:0] blue,
);
wire [9:0] h_counter;
wire [9:0] v_counter;
wire [3:0] internal_red;
wire [3:0] internal_green;
wire [3:0] internal_blue;
assign hsync = (h_counter < 92) ? 1'b1 : 1'b0;
assign vsync = (v_counter < 2) ? 1'b1 : 1'b0;
assign active = 143 < h_counter && h_counter < 784 && 34 < v_counter && v_counter < 515;
assign red = active ? internal_red : 4'h0;
assign green = active ? internal_green : 4'h0;
assign blue = active ? internal_blue : 4'h0;
sync_counter (clk, rst, h_counter, v_counter);
color_control (h_counter, v_counter, x, y, block_data, block_position, internal_red, internal_green, internal_blue);
endmodule
module sync_counter(
input clk,
input rst,
output reg [9:0] h_counter;
output reg [9:0] v_counter;
);
always @(posedge clk or negedge rst) begin
if (~rst) begin
h_counter <= 0;
v_counter <= 0;
end else begin
if (h_counter <= 799) begin
h_counter <= h_counter + 1;
end else begin
h_counter <= 0;
end
if (v_counter <= 524) begin
if (h_counter == 0) begin
v_counter <= v_counter + 1;
end else begin
v_counter <= v_counter;
end
end else begin
v_counter <= 0;
end
end
end
endmodule
module color_control(
input [9:0] h_counter,
input [9:0] v_counter,
input [3:0] x,
input [3:0] y,
input [5:0] block_data,
output [9:0] block_position,
output reg [3:0] red,
output reg [3:0] green,
output reg [3:0] blue
);
wire [3:0] row_coor, col_coor;
wire [5:0] i_val, j_val;
/* color:
0: white
1: black
2: gray
*/
reg [1:0] color;
reg [2:0] block_type;
assign col_coor = (h_counter - 144) / 64;
assign row_coor = (v_counter - 35) / 48;
assign block_position = row_coor * 10 + col_coor;
assign j_val = (h_counter - 144) % 64;
assign i_val = (v_counter - 35) % 48;
always @(*) begin
if(col_coor >= 10 || row_coor >= 10) begin
color <= 2;
end else begin
block_type <= block_data & 6'b000111;
case(block_type)
4'd0: begin
if((0 <= i_val && i_val <= 3) || (44 <= i_val && i_val <= 47) || (0 <= j_val && j_val <= 3) || (60 <= j_val && j_val <= 63))
color <= 1;
else if(23 <= i_val && i_val <= 26 && 27 <= j_val && j_val <= 38)
color <= 1;
else
color <= 2;
end
4'd1: begin
if((0 <= i_val && i_val <= 3) || (44 <= i_val && i_val <= 47) || (0 <= j_val && j_val <= 3) || (60 <= j_val && j_val <= 63))
color <= 1;
else if(11 <= i_val && i_val <= 38 && 39 <= j_val && j_val <= 42)
color <= 1;
else
color <= 2;
end
4'd2: begin
if((0 <= i_val && i_val <= 3) || (44 <= i_val && i_val <= 47) || (0 <= j_val && j_val <= 3) || (60 <= j_val && j_val <= 63))
color <= 1;
else if(7 <= i_val && i_val <= 10 && 27 <= j_val && j_val <= 38)
color <= 1;
else if(11 <= i_val && i_val <= 22 && 39 <= j_val && j_val <= 42)
color <= 1;
else if(23 <= i_val && i_val <= 26 && 27 <= j_val && j_val <= 38)
color <= 1;
else if(27 <= i_val && i_val <= 38 && 23 <= j_val && j_val <= 26)
color <= 1;
else if(39 <= i_val && i_val <= 42 && 27 <= j_val && j_val <= 38)
color <= 1;
else
color <= 2;
end
4'd3: begin
if((0 <= i_val && i_val <= 3) || (44 <= i_val && i_val <= 47) || (0 <= j_val && j_val <= 3) || (60 <= j_val && j_val <= 63))
color <= 1;
else if(7 <= i_val && i_val <= 10 && 27 <= j_val && j_val <= 38)
color <= 1;
else if(11 <= i_val && i_val <= 22 && 39 <= j_val && j_val <= 42)
color <= 1;
else if(23 <= i_val && i_val <= 26 && 27 <= j_val && j_val <= 38)
color <= 1;
else if(27 <= i_val && i_val <= 38 && 39 <= j_val && j_val <= 42)
color <= 1;
else if(39 <= i_val && i_val <= 42 && 27 <= j_val && j_val <= 38)
color <= 1;
else
color <= 2;
end
4'd4: begin
if((0 <= i_val && i_val <= 3) || (44 <= i_val && i_val <= 47) || (0 <= j_val && j_val <= 3) || (60 <= j_val && j_val <= 63))
color = 1;
else if(11 <= i_val && i_val <= 22 && (23 <= j_val && j_val <= 26 || 39 <= j_val && j_val <= 42))
color <= 1;
else if(23 <= i_val && i_val <= 26 && 27 <= j_val && j_val <= 38)
color <= 1;
else if(27 <= i_val && i_val <= 38 && 39 <= j_val && j_val <= 42)
color <= 1;
else
color <= 2;
end
default: color <= (0 <= i_val && i_val <= 3) || (44 <= i_val && i_val <= 47) || (0 <= j_val && j_val <= 3) || (60 <= j_val && j_val <= 63) ? 1 : 2;
endcase
end
case(color)
2'b00: begin
red <= 4'b0000;
green <= 4'b0000;
blue <= 4'b0000;
end
2'b01: begin
red <= 4'b1111;
green <= 4'b1111;
blue <= 4'b1111;
end
default: begin
if (x == col_coor && y == row_coor) begin
red <= 4'b0111;
green <= 4'b0111;
blue <= 4'b0000;
end else begin
red <= 4'b0101;
green <= 4'b0101;
blue <= 4'b0101;
end
end
endcase
end
endmodule
```
## Bitmap
:::spoiler 8
```
{
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000011111111111100000000000000000000001111,
64'b1111000000000000000000000011111111111100000000000000000000001111,
64'b1111000000000000000000000011111111111100000000000000000000001111,
64'b1111000000000000000000000011111111111100000000000000000000001111,
64'b1111000000000000000000111100000000000011110000000000000000001111,
64'b1111000000000000000000111100000000000011110000000000000000001111,
64'b1111000000000000000000111100000000000011110000000000000000001111,
64'b1111000000000000000000111100000000000011110000000000000000001111,
64'b1111000000000000000000111100000000000011110000000000000000001111,
64'b1111000000000000000000111100000000000011110000000000000000001111,
64'b1111000000000000000000111100000000000011110000000000000000001111,
64'b1111000000000000000000111100000000000011110000000000000000001111,
64'b1111000000000000000000111100000000000011110000000000000000001111,
64'b1111000000000000000000111100000000000011110000000000000000001111,
64'b1111000000000000000000111100000000000011110000000000000000001111,
64'b1111000000000000000000111100000000000011110000000000000000001111,
64'b1111000000000000000000000011111111111100000000000000000000001111,
64'b1111000000000000000000000011111111111100000000000000000000001111,
64'b1111000000000000000000000011111111111100000000000000000000001111,
64'b1111000000000000000000000011111111111100000000000000000000001111,
64'b1111000000000000000000111100000000000011110000000000000000001111,
64'b1111000000000000000000111100000000000011110000000000000000001111,
64'b1111000000000000000000111100000000000011110000000000000000001111,
64'b1111000000000000000000111100000000000011110000000000000000001111,
64'b1111000000000000000000111100000000000011110000000000000000001111,
64'b1111000000000000000000111100000000000011110000000000000000001111,
64'b1111000000000000000000111100000000000011110000000000000000001111,
64'b1111000000000000000000111100000000000011110000000000000000001111,
64'b1111000000000000000000111100000000000011110000000000000000001111,
64'b1111000000000000000000111100000000000011110000000000000000001111,
64'b1111000000000000000000111100000000000011110000000000000000001111,
64'b1111000000000000000000111100000000000011110000000000000000001111,
64'b1111000000000000000000000001111111111100000000000000000000001111,
64'b1111000000000000000000000001111111111100000000000000000000001111,
64'b1111000000000000000000000001111111111100000000000000000000001111,
64'b1111000000000000000000000001111111111100000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111
}
```
:::
:::spoiler 7
```
{
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000011111111111100000000000000000000001111,
64'b1111000000000000000000000011111111111100000000000000000000001111,
64'b1111000000000000000000000011111111111100000000000000000000001111,
64'b1111000000000000000000000011111111111100000000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111
}
```
:::
:::spoiler 6
```
{
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000011111111111100000000000000000000001111,
64'b1111000000000000000000000011111111111100000000000000000000001111,
64'b1111000000000000000000000011111111111100000000000000000000001111,
64'b1111000000000000000000000011111111111100000000000000000000001111,
64'b1111000000000000000000111100000000000000000000000000000000001111,
64'b1111000000000000000000111100000000000000000000000000000000001111,
64'b1111000000000000000000111100000000000000000000000000000000001111,
64'b1111000000000000000000111100000000000000000000000000000000001111,
64'b1111000000000000000000111100000000000000000000000000000000001111,
64'b1111000000000000000000111100000000000000000000000000000000001111,
64'b1111000000000000000000111100000000000000000000000000000000001111,
64'b1111000000000000000000111100000000000000000000000000000000001111,
64'b1111000000000000000000111100000000000000000000000000000000001111,
64'b1111000000000000000000111100000000000000000000000000000000001111,
64'b1111000000000000000000111100000000000000000000000000000000001111,
64'b1111000000000000000000111100000000000000000000000000000000001111,
64'b1111000000000000000000000011111111111100000000000000000000001111,
64'b1111000000000000000000000011111111111100000000000000000000001111,
64'b1111000000000000000000000011111111111100000000000000000000001111,
64'b1111000000000000000000000011111111111100000000000000000000001111,
64'b1111000000000000000000111100000000000011110000000000000000001111,
64'b1111000000000000000000111100000000000011110000000000000000001111,
64'b1111000000000000000000111100000000000011110000000000000000001111,
64'b1111000000000000000000111100000000000011110000000000000000001111,
64'b1111000000000000000000111100000000000011110000000000000000001111,
64'b1111000000000000000000111100000000000011110000000000000000001111,
64'b1111000000000000000000111100000000000011110000000000000000001111,
64'b1111000000000000000000111100000000000011110000000000000000001111,
64'b1111000000000000000000111100000000000011110000000000000000001111,
64'b1111000000000000000000111100000000000011110000000000000000001111,
64'b1111000000000000000000111100000000000011110000000000000000001111,
64'b1111000000000000000000111100000000000011110000000000000000001111,
64'b1111000000000000000000000001111111111100000000000000000000001111,
64'b1111000000000000000000000001111111111100000000000000000000001111,
64'b1111000000000000000000000001111111111100000000000000000000001111,
64'b1111000000000000000000000001111111111100000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111
}
```
:::
:::spoiler 5
```
{
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000011111111111100000000000000000000001111,
64'b1111000000000000000000000011111111111100000000000000000000001111,
64'b1111000000000000000000000011111111111100000000000000000000001111,
64'b1111000000000000000000000011111111111100000000000000000000001111,
64'b1111000000000000000000111100000000000000000000000000000000001111,
64'b1111000000000000000000111100000000000000000000000000000000001111,
64'b1111000000000000000000111100000000000000000000000000000000001111,
64'b1111000000000000000000111100000000000000000000000000000000001111,
64'b1111000000000000000000111100000000000000000000000000000000001111,
64'b1111000000000000000000111100000000000000000000000000000000001111,
64'b1111000000000000000000111100000000000000000000000000000000001111,
64'b1111000000000000000000111100000000000000000000000000000000001111,
64'b1111000000000000000000111100000000000000000000000000000000001111,
64'b1111000000000000000000111100000000000000000000000000000000001111,
64'b1111000000000000000000111100000000000000000000000000000000001111,
64'b1111000000000000000000111100000000000000000000000000000000001111,
64'b1111000000000000000000000011111111111100000000000000000000001111,
64'b1111000000000000000000000011111111111100000000000000000000001111,
64'b1111000000000000000000000011111111111100000000000000000000001111,
64'b1111000000000000000000000011111111111100000000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000001111111111100000000000000000000001111,
64'b1111000000000000000000000001111111111100000000000000000000001111,
64'b1111000000000000000000000001111111111100000000000000000000001111,
64'b1111000000000000000000000001111111111100000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111
}
```
:::
:::spoiler 4
```
{
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000111100000000000011110000000000000000001111,
64'b1111000000000000000000111100000000000011110000000000000000001111,
64'b1111000000000000000000111100000000000011110000000000000000001111,
64'b1111000000000000000000111100000000000011110000000000000000001111,
64'b1111000000000000000000111100000000000011110000000000000000001111,
64'b1111000000000000000000111100000000000011110000000000000000001111,
64'b1111000000000000000000111100000000000011110000000000000000001111,
64'b1111000000000000000000111100000000000011110000000000000000001111,
64'b1111000000000000000000111100000000000011110000000000000000001111,
64'b1111000000000000000000111100000000000011110000000000000000001111,
64'b1111000000000000000000111100000000000011110000000000000000001111,
64'b1111000000000000000000111100000000000011110000000000000000001111,
64'b1111000000000000000000000011111111111100000000000000000000001111,
64'b1111000000000000000000000011111111111100000000000000000000001111,
64'b1111000000000000000000000011111111111100000000000000000000001111,
64'b1111000000000000000000000011111111111100000000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111
}
```
:::
:::spoiler 3
```
{
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000011111111111100000000000000000000001111,
64'b1111000000000000000000000011111111111100000000000000000000001111,
64'b1111000000000000000000000011111111111100000000000000000000001111,
64'b1111000000000000000000000011111111111100000000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000011111111111100000000000000000000001111,
64'b1111000000000000000000000011111111111100000000000000000000001111,
64'b1111000000000000000000000011111111111100000000000000000000001111,
64'b1111000000000000000000000011111111111100000000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000001111111111100000000000000000000001111,
64'b1111000000000000000000000001111111111100000000000000000000001111,
64'b1111000000000000000000000001111111111100000000000000000000001111,
64'b1111000000000000000000000001111111111100000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111
}
```
:::
:::spoiler 2
```
{
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000011111111111100000000000000000000001111,
64'b1111000000000000000000000011111111111100000000000000000000001111,
64'b1111000000000000000000000011111111111100000000000000000000001111,
64'b1111000000000000000000000011111111111100000000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000011111111111100000000000000000000001111,
64'b1111000000000000000000000011111111111100000000000000000000001111,
64'b1111000000000000000000000011111111111100000000000000000000001111,
64'b1111000000000000000000000011111111111100000000000000000000001111,
64'b1111000000000000000000111100000000000000000000000000000000001111,
64'b1111000000000000000000111100000000000000000000000000000000001111,
64'b1111000000000000000000111100000000000000000000000000000000001111,
64'b1111000000000000000000111100000000000000000000000000000000001111,
64'b1111000000000000000000111100000000000000000000000000000000001111,
64'b1111000000000000000000111100000000000000000000000000000000001111,
64'b1111000000000000000000111100000000000000000000000000000000001111,
64'b1111000000000000000000111100000000000000000000000000000000001111,
64'b1111000000000000000000111100000000000000000000000000000000001111,
64'b1111000000000000000000111100000000000000000000000000000000001111,
64'b1111000000000000000000111100000000000000000000000000000000001111,
64'b1111000000000000000000111100000000000000000000000000000000001111,
64'b1111000000000000000000000001111111111100000000000000000000001111,
64'b1111000000000000000000000001111111111100000000000000000000001111,
64'b1111000000000000000000000001111111111100000000000000000000001111,
64'b1111000000000000000000000001111111111100000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111
}
```
:::
:::spoiler 1
```
{
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000011110000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111
}
```
:::
:::spoiler empty
```
{
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111
}
```
:::
:::spoiler bomb
```
{
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000011111100000000000000000000001111,
64'b1111000000000000000000000000001111111111000000000110000000001111,
64'b1111000000000000000000000000011110001111100000001110000000001111,
64'b1111000000000000000000000000111100000011110000001110000000001111,
64'b1111000000000000000000000000111000000001111000011100000000001111,
64'b1111000000000000000000000001111000000000111111111000000000001111,
64'b1111000000000000000000000111111110000000001111110000000000001111,
64'b1111000000000000000000111111111111110000000000000000000000001111,
64'b1111000000000000000001111100000011111000000000000000000000001111,
64'b1111000000000000000011100000000000011100000000000000000000001111,
64'b1111000000000000000111000000000000001110000000000000000000001111,
64'b1111000000000000001110000000000000000111000000000000000000001111,
64'b1111000000000000011100000000000000000011100000000000000000001111,
64'b1111000000000000111000000000000000000001110000000000000000001111,
64'b1111000000000000110000000000000000000000110000000000000000001111,
64'b1111000000000000110000000000000000000000110000000000000000001111,
64'b1111000000000001110000000000000000000000111000000000000000001111,
64'b1111000000000001100000000000000000000000011000000000000000001111,
64'b1111000000000001100000000000000000000000011000000000000000001111,
64'b1111000000000001100000000000000000000000011000000000000000001111,
64'b1111000000000001100000000000000000000000011000000000000000001111,
64'b1111000000000001100000000000000000000000011000000000000000001111,
64'b1111000000000001100000000000000000000000011000000000000000001111,
64'b1111000000000001110000000000000000000000111000000000000000001111,
64'b1111000000000000110000000000000000000000110000000000000000001111,
64'b1111000000000000110000000000000000000000110000000000000000001111,
64'b1111000000000000111000000000000000000001110000000000000000001111,
64'b1111000000000000011100000000000000000011100000000000000000001111,
64'b1111000000000000001110000000000000000111000000000000000000001111,
64'b1111000000000000000111000000000000001110000000000000000000001111,
64'b1111000000000000000011100000000000011100000000000000000000001111,
64'b1111000000000000000001111100000011111000000000000000000000001111,
64'b1111000000000000000000111111111111110000000000000000000000001111,
64'b1111000000000000000000000111111110000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111000000000000000000000000000000000000000000000000000000001111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111,
64'b1111111111111111111111111111111111111111111111111111111111111111
}
```
:::
:::spoiler vga code
- vga_driver
```verilog=
module vga_driver(clk, Hsynq, Vsynq, Red, Green, Blue, reset);
input clk, reset;
output Hsynq, Vsynq;
output [3:0] Red, Green, Blue;
wire clk_25Mhz;
wire enable_V_Counter;
wire [15:0] H_Count_Value, V_Count_Value;
wire [3:0] val_red, val_green, val_blue;
wire active;
clock_divider (clk, clk_25Mhz);
horizontal_counter (clk_25Mhz, enable_V_Counter, H_Count_Value);
vertical_counter (clk_25Mhz, enable_V_Counter, V_Count_Value);
color_control (H_Count_Value, V_Count_Value, val_red, val_green, val_blue);
assign Hsynq = (H_Count_Value < 92) ? 1'b1 : 1'b0;
assign Vsynq = (V_Count_Value < 2) ? 1'b1 : 1'b0;
assign active = 143 < H_Count_Value && H_Count_Value < 784 && 34 < V_Count_Value && V_Count_Value < 515;
assign Red = active ? val_red : 4'h0;
assign Green = active ? val_green : 4'h0;
assign Blue = active ? val_blue : 4'h0;
endmodule
```
- color control
```verilog=
module color_control(hcounter, vcounter, val_red, val_green, val_blue);
input [15:0] hcounter, vcounter;
output reg [3:0] val_red = 0, val_green = 0, val_blue = 0;
wire [3:0] row_coor, col_coor;
wire [5:0] i_val, j_val;
reg [1:0] color; // 0: white, 1: black, 2: grey;
reg [2:0] block_type;
assign col_coor = (hcounter - 144) / 64;
assign row_coor = (vcounter - 35) / 48;
assign j_val = (hcounter - 144) % 64;
assign i_val = (vcounter - 35) % 48;
always @(*) begin
if(col_coor >= 10 || row_coor >= 10) begin
color = 2;
end
else begin
block_type = 0;
case(block_type)
4'd0: begin
if((0 <= i_val && i_val <= 3) || (44 <= i_val && i_val <= 47) || (0 <= j_val && j_val <= 3) || (60 <= j_val && j_val <= 63))
color = 1;
else if(23 <= i_val && i_val <= 26 && 27 <= j_val && j_val <= 38)
color = 1;
else
color = 2;
end
4'd1: begin
if((0 <= i_val && i_val <= 3) || (44 <= i_val && i_val <= 47) || (0 <= j_val && j_val <= 3) || (60 <= j_val && j_val <= 63))
color = 1;
else if(11 <= i_val && i_val <= 38 && 39 <= j_val && j_val <= 42)
color = 1;
else
color = 2;
end
4'd2: begin
if((0 <= i_val && i_val <= 3) || (44 <= i_val && i_val <= 47) || (0 <= j_val && j_val <= 3) || (60 <= j_val && j_val <= 63))
color = 1;
else if(7 <= i_val && i_val <= 10 && 27 <= j_val && j_val <= 38)
color = 1;
else if(11 <= i_val && i_val <= 22 && 39 <= j_val && j_val <= 42)
color = 1;
else if(23 <= i_val && i_val <= 26 && 27 <= j_val && j_val <= 38)
color = 1;
else if(27 <= i_val && i_val <= 38 && 23 <= j_val && j_val <= 26)
color = 1;
else if(39 <= i_val && i_val <= 42 && 27 <= j_val && j_val <= 38)
color = 1;
else
color = 2;
end
4'd3: begin
if((0 <= i_val && i_val <= 3) || (44 <= i_val && i_val <= 47) || (0 <= j_val && j_val <= 3) || (60 <= j_val && j_val <= 63))
color = 1;
else if(7 <= i_val && i_val <= 10 && 27 <= j_val && j_val <= 38)
color = 1;
else if(11 <= i_val && i_val <= 22 && 39 <= j_val && j_val <= 42)
color = 1;
else if(23 <= i_val && i_val <= 26 && 27 <= j_val && j_val <= 38)
color = 1;
else if(27 <= i_val && i_val <= 38 && 39 <= j_val && j_val <= 42)
color = 1;
else if(39 <= i_val && i_val <= 42 && 27 <= j_val && j_val <= 38)
color = 1;
else
color = 2;
end
4'd4: begin
if((0 <= i_val && i_val <= 3) || (44 <= i_val && i_val <= 47) || (0 <= j_val && j_val <= 3) || (60 <= j_val && j_val <= 63))
color = 1;
else if(11 <= i_val && i_val <= 22 && (23 <= j_val && j_val <= 26 || 39 <= j_val && j_val <= 42))
color = 1;
else if(23 <= i_val && i_val <= 26 && 27 <= j_val && j_val <= 38)
color = 1;
else if(27 <= i_val && i_val <= 38 && 39 <= j_val && j_val <= 42)
color = 1;
else
color = 2;
end
default: color = (0 <= i_val && i_val <= 3) || (44 <= i_val && i_val <= 47) || (0 <= j_val && j_val <= 3) || (60 <= j_val && j_val <= 63) ? 1 : 2;
endcase
end
end
always @(*) begin
case(color)
2'b00: begin
val_red <= 4'b0000;
val_green <= 4'b0000;
val_blue <= 4'b0000;
end
2'b01: begin
val_red <= 4'b1111;
val_green <= 4'b1111;
val_blue <= 4'b1111;
end
default: begin
val_red <= 4'b0101;
val_green <= 4'b0101;
val_blue <= 4'b0101;
end
endcase
end
endmodule
```
- vertical counter
```verilog=
module vertical_counter(clk_25Mhz, enable_V_Counter, V_Count_Value);
input clk_25Mhz, enable_V_Counter;
output reg [15:0] V_Count_Value = 0;
always @(posedge clk_25Mhz) begin
if( enable_V_Counter == 1'b1) begin
if(V_Count_Value < 524) begin
V_Count_Value <= V_Count_Value + 1;
end
else begin
V_Count_Value <= 0;
end
end
end
endmodule
```
- horizontal conter
```verilog=
module vertical_counter(clk_25Mhz, enable_V_Counter, V_Count_Value);
input clk_25Mhz, enable_V_Counter;
output reg [15:0] V_Count_Value = 0;
always @(posedge clk_25Mhz) begin
if( enable_V_Counter == 1'b1) begin
if(V_Count_Value < 524) begin
V_Count_Value <= V_Count_Value + 1;
end
else begin
V_Count_Value <= 0;
end
end
end
endmodule
```
- clock divider
```verilog=
module vertical_counter(clk_25Mhz, enable_V_Counter, V_Count_Value);
input clk_25Mhz, enable_V_Counter;
output reg [15:0] V_Count_Value = 0;
always @(posedge clk_25Mhz) begin
if( enable_V_Counter == 1'b1) begin
if(V_Count_Value < 524) begin
V_Count_Value <= V_Count_Value + 1;
end
else begin
V_Count_Value <= 0;
end
end
end
endmodule
```
:::
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