###### tags: `Lógica Digital`
# SÍNTESE DE CIRCUITOS - MÁQUINA DE ESTADOS FINITOS
## Máquina de Moore
### Exemplo 1
#### Verilog - Comportamental
```verilog
module maquina_moore(Clock, Resetn, w, z);
input Clock, Resetn, w;
output z;
reg[2:1] y, Y; //Sendo y o atual e Y o seguinte
parameter [2:1] A = 2'b00, B = 2'b01, C = 2'b10;
//Define o próximo estado combinacional do circuito
always @(w, y)
case(y)
A: if(w) Y = B;
else Y = A;
B: if(w) Y = C;
else Y = B;
C: if(w) Y = C;
else Y = A;
default: Y = 2'bxx;
endecase
//Define o bloco sequencial
always @(negedge Resetn, posedge Clock)
if(Resetn == 0) y <= A;
else y <= Y;
assign z = (y == C);
endmodule
```
Alternativa
```verilog
module simple (Clock, Resetn, w, z);
input Clock, Resetn, w;
output z;
reg [2:1] y;
parameter [2:1] A = 2'b00, B = 2'b01, C = 2'b10;
// Define the sequential block
always @(negedge Resetn, posedge Clock)
if (Resetn == 0) y <= A;
else
case (y)
A: if (w) y <= B;
else y <= A;
B: if (w) y <= C;
else y <= A;
C: if (w) y <= C;
else y <= A;
default: y <= 2'bxx;
endcase
// Define output
assign z = (y == C);
endmodule
```
#### Verilog- Estrutural
Dada tabela de atribuição de estados modificada e o diagrama do circuito
```verilog
// Structural design
module fsm (
input clk, rst, w,
output z);
wire Y1, Y2;
//module dff(input clk, rst, d, output reg q, nq);
dff y1 (clk, rst, w, Y1);
dff y2 (clk, rst, Y1, Y2);
and (z, Y1, Y2);
endmodule
// Flip-flop D
module dff(
input clk, rst, d,
output reg q, nq);
always@(posedge clk or posedge rst)
if (rst)
q = 0;
else
q = d;
assign nq = !q;
endmodule
```
---
## Máquina de Mealy
### Exemplo 1
#### Verilog - Comportamental
```verilog
module mealy (Clock, Resetn, w, z);
input Clock, Resetn, w;
output reg z;
reg y, Y;
parameter A = 1'b0, B = 1'b1;
// Define the next state and output combinational circuits
always @(w, y)
case (y)
A: if (w) begin
z = 0;
Y = B;
end
else begin
z = 0;
Y = A;
end
B: if (w) begin
z = 1;
Y = B;
end
else begin
z = 0;
Y = A;
end
endcase
// Define the sequential block
always @(negedge Resetn, posedge Clock)
if (Resetn = = 0) y <= A;
else
y <= Y;
endmodule
```
---
## Semáforo para pedestres
### Gabarito verilog
```verilog
module top (clk, rst, BT, stA, stB, count, t5s, t15s, t20s, t50s, zcp, zc, y, Y);
parameter n = 6;
input clk, rst, BT;
output [3:1] stA, stB;
output [n-1:0] count;
output reg [3:1] y, Y;
output t5s, t15s, t20s, t50s, zcp, zc;
traffic light(clk, rst, BT, t5s, t15s, t20s, t50s, stA, stB, zcp, zc, y, Y);
counter #(n) c(clk, rst | zcp, count);
assign t5s = count == 6'b000011; // 5-2
assign t15s = count == 6'b001101; // 15-2
assign t20s = count == 6'b010010; // 20-2
assign t50s = count == 6'b110000; // 50-2
endmodule
module traffic (clk, rst, BT, t5s, t15s, t20s, t50s, stA, stB, zcp, zc, y, Y);
input clk, rst, BT, t5s, t15s, t20s, t50s;
output [3:1] stA, stB;
output zcp;
output zc;
output reg [3:1] y, Y;
wire [3:1] red_blink;
parameter [3:1] A = 3'b000, B = 3'b001, C = 3'b010, D = 3'b011, A1 = 3'b100, A2 = 3'b101;
parameter red=3'b100, yellow=3'b010, green=3'b001;
pulse p(clk, zc, zcp);
// Define the next state combinational circuit
always @(BT, t5s, t15s, t20s, t50s, y)
case (y)
A: if (BT) Y = B;
else Y = A;
A1:if (t50s) Y = A;
else
if (BT) Y = A2;
else Y = A1;
A2:if (t50s) Y = B;
else Y = A2;
B: if (t5s) Y = C;
else Y = B;
C: if (t15s) Y = D;
else Y = C;
D: if (t20s) Y = A1;
else Y = D;
default: Y = 2'bxx;
endcase
// Define the sequential block
always @(posedge rst, posedge clk)
if (rst) y <= A;
else y <= Y;
// Define output
assign red_blink = red & {clk, 2'b0};
assign stA = y == C ? green : (y == D ? red_blink : red);
assign stB = (y == A | y == A1 | y == A2) ? green : (y == B ? yellow : red);
assign zc = (y == B);
endmodule
module counter (clk, rst, count);
parameter n = 8;
input clk, rst;
output reg [n-1:0] count;
always@(posedge clk or rst)
if (rst)
count = 0;
else
count = count + 1;
endmodule
module pulse(clk, in, out);
input clk, in;
output out;
reg [1:0] s;
always@(posedge clk)
s <= {in, s[1]};
assign out = s[1] & ~s[0];
endmodule
```
---
## Elevador
### Gabarito verilog
```verilog
// Behavioral design ////////////////////////////////////////
module b_elevator (clk, rst, P0, P1, B0, B1, S0, S1, MD, MS);
input clk, rst, P0, P1, B0, B1, S0, S1;
output MD, MS;
reg [2:1] y, Y;
parameter Baixo = 2'b00, Subindo = 2'b01, Cima = 2'b10, Descendo = 2'b11;
// Define the next state combinational circuit
always @(P0, P1, B0, B1, S0, S1, y)
case (y)
Baixo:
if (B1) Y = Subindo;
else Y = Baixo;
Subindo:
if (S1) Y = Cima;
else Y = Subindo;
Cima:
if (B0) Y = Descendo;
else Y = Cima;
Descendo:
if (S0) Y = Baixo;
else Y = Descendo;
default: Y = 2'bxx;
endcase
// Define the sequential block
always @(negedge rst, posedge clk)
if (rst) y <= Baixo;
else y <= Y;
// Define output
assign MD = y == Descendo;
assign MS = y == Subindo;
endmodule
// Structural design ////////////////////////////////////////
module s_elevator (clk, rst, P0, P1, B0, B1, S0, S1, MD, MS, Y);
input clk, rst, P0, P1, B0, B1, S0, S1;
output MD, MS;
output reg [4:1] Y;
parameter Baixo = 4'b1000, Subindo = 4'b0100,
Cima = 4'b0010, Descendo = 4'b0001;
// Define the expressions
always @(negedge rst, posedge clk)
if (rst) Y <= Baixo;
else
begin
Y[4] <= Y[1] & S0 | Y[4] & ~B1;
Y[3] <= Y[4] & B1 | Y[3] & ~S1;
Y[2] <= Y[3] & S1 | Y[2] & ~B0;
Y[1] <= Y[2] & B0 | Y[1] & ~S0;
end;
// Define output
assign MD = Y == Descendo;
assign MS = Y == Subindo;
endmodule
```
---
## Minimização
### Exemplo 1
A máquina resultante :
### Exemplo 2
### Exemplo 3
---
## Barramentos
### Buffer tristate
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