NAME : BHUKYA LACHIRAM NAYAK
ROLL NO : CS22B012
LAB 8:

**question 1**

module halfAdder(y,c,a,b);

input a,b;
output s,carry;

assign s=(~a&b)|(~b&a);
assign carry=a&b;
endmodule

**question 1**

  module fullAdder(a,b,c,s,cout);

input a,b,cin;
output s,cout;
wire c1,c2,s1;

halfAdder HA1(.a(a),.b(b),,s(s1),.carry(c1));
halfAdder HA2(.a(a),.b(b),,s(s),.carry(c2));
assign cout = c1|c2;

endmodule

**question 1**

 module FA_testbench();
    
reg a1,b1,c1;
wire y1,y2;

fullAdder DUT1(.a(a1),.b(b1),.c(c1),.y=s(y1),.cout(y2));

initial 

begin 
a1 = 1'b0; b1=1'b0; c1=1'b0;

#100 a1 = 1'b0; b1=1'b0; c1=1'b1;
#100 a1 = 1'b0; b1=1'b1; c1=1'b0;
#100 a1 = 1'b0; b1=1'b1; c1=1'b1;
#100 a1 = 1'b1; b1=1'b0; c1=1'b0;
#100 a1 = 1'b1; b1=1'b0; c1=1'b1;
#100 a1 = 1'b1; b1=1'b1; c1=1'b0;
#100 a1 = 1'b1; b1=1'b1; c1=1'b1;
end
endmodule
 

**question 2**

  
  module rippleAdder(
    input [3:0] a,
    input [3:0] b,
    input cin,
    output [3:0] sum,
    output cout
);

wire [3:0] carry;
wire c0, c1, c2;

fullAdder FA0(.a(a[0]), .b(b[0]), .c(cin), .s(sum[0]), .cout(c0));
fullAdder FA1(.a(a[1]), .b(b[1]), .c(c0), .s(sum[1]), .cout(c1));
fullAdder FA2(.a(a[2]), .b(b[2]), .c(c1), .s(sum[2]), .cout(c2));
fullAdder FA3(.a(a[3]), .b(b[3]), .c(c2), .s(sum[3]), .cout(carry[3]));

assign cout = carry[3];

endmodule

**question 2**

   
   module RA_testbench;

reg [3:0] a, b;
reg cin;
wire [3:0] sum;
wire cout;

rippleAdder RCA(
    .a(a),
    .b(b),
    .cin(cin),
    .sum(sum),
    .cout(cout)
);

initial begin
    // some permutations of inputs
    a = 4'b0000; b = 4'b0000; cin = 0; #100; // 0 + 0 = 0
    a = 4'b1010; b = 4'b0101; cin = 0; #100; // 10 + 5 = 15
    a = 4'b1111; b = 4'b0001; cin = 1; #100; // 15 + 1 (with carry) = 17
    a = 4'b1100; b = 4'b0011; cin = 0; #100; // 12 + 3 = 15
    a = 4'b1010; b = 4'b1010; cin = 1; #100; // 10 + 10 (with carry) = 21
end
endmodule

**question 3**

  
  module mux(y,s1,d1,d2);

input s1,d1,d2;
output y;
wire y1,y2;

assign y1 = ~s1&d1;
assign y2 = s1&s2;
assign y = y1|y2;

endmodule
  

**question 3**

   module mux_bench();

reg d1,d2,s1;

wire y1;

mux DUT1(.s1(s1),.d1(d1),.d2(d2),.y(y1));

initial 

begin 

d1=1'b0; d2=1'b1;

s1 = 1'b0;
#100 s1 = 1'b1;
end
endmodule