# Lab 6 Advanced FPGA - Dual FPGA Communication

## Requirements

1. Please design a simple FPGA-to-FPGA Communication protocol.

2. The protocol have to fulfill the following requirements:
- Use the Handshaking protocol to send a number from Master FPGA to Slave FPGA:
- Master -> Slave request
- Slave -> Master ACK
- Master -> Slave send data (number)

3. Your design should in an observable speed so that TAs can know whether your design is correct or not

4. Your design should be stable and should avoid signal loss.

## Data representation
- For **Master FPGA**, use switches to determine the number in one-hot form
- For **Slave FPGA**, show the number on 7-segment displays.
- Please illuminate the LED[0] for **at least 1 second** when FPGA receive a request or an ACK.
- Below are switches input and the corresponding 7-segment display.

## Button control
- The UP button is for **reset**, and the MIDDLE button is for **sending request**
- The communication starts only after the **send request** button on master FPGA is pressed.
- On **Master FPGA reset**, it stops communicate with slave until the next send request button is pressed.
- On **Slave FPGA reset**, the 7-segment display 0 until next request.
- The reset action of the two FPGA is independent of each other.

## Communication Process
- The whole communicate process is designed as below:
- The display on the Slave FPGA should be hold until the data of next request is received.

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## Ports Connection via Jumper
- Below is a demonstration of ports connection via jumper as defined in the XDC file provided.
- In case some ports are malfunctioning, you are also allow to use other ports, as long as the FPGAs can communicate correctly according to spec.
- Reference for FPGA port mapping: https://reference.digilentinc.com/_media/basys3/basys3-pinout.png