# Iverilog

Introduction
---
Icarus Verilog is an implementation of the Verilog hardware description language compiler that generates netlists in the desired format and a simulator. It supports the 1995, 2001 and 2005 versions of the standard, portions of SystemVerilog, and some extensions.

Verilog
---
Verilog, standardized as IEEE 1364, is a hardware description language used to model electronic systems. It is most commonly used in the design and verification of digital circuits at the register-transfer level of abstraction.

Verilog Syntax
----

How to install
---
https://zhuanlan.zhihu.com/p/436976157?utm_id=0

1. First go to http://bleyer.org/icarus/ and download the latest stable release.

2. Install icarus on your pc

3. Add it to windows path

- Go to the control panel and select System and Security

- Click on System

- Click on Advance System Settings

- Click on Enviorment Variables

- Click on PATH and then edit

- Click on browse and choose the bin file of where you installed iverilog

- Test it on your command line

Usage
----

Code
---

module up_counter(input clk, reset, output[3:0] counter
    );
reg [3:0] counter_up;

// up counter
always @(posedge clk or posedge reset)
begin
if(reset)
 counter_up <= 4'd0;
else
 counter_up <= counter_up + 4'd1;
end 
assign counter = counter_up;
endmodule

// upcounter_testbench.v
module upcounter_testbench;
  reg clk, reset;
  wire [3:0] counter;

  up_counter dut(clk, reset, counter);

  // Initial block for testbench
  initial begin
    // Open VCD file for waveform dumping
    $dumpfile("waveform.vcd");
    
    // Dump signals to VCD file
    $dumpvars(0, upcounter_testbench);

    // Initialize signals
    clk = 0;
    reset = 1;

    // Apply reset and toggle clock
    #20;
    reset = 0;
    forever #5 clk = ~clk;
  end
endmodule

iverilog -o counter up_counter.v upcounter_testbench.v
vvp counter
gtkwave waveform.vcd


// inverter.v
module inverter (
  input wire a,
  output reg y
);

  always @(a)
    y <= ~a;

endmodule

// tb_inverter.v
module tb_inverter;

  // Inputs
  reg a;

  // Outputs
  wire y;

  // Instantiate the inverter
  inverter uut (
    .a(a),
    .y(y)
  );

  // Initial block for testbench
  initial begin
    // Open VCD file for waveform dumping
    $dumpfile("waveform.vcd");
    
    // Dump signals to VCD file
    $dumpvars(0, tb_inverter);

    // Test case 1
    a = 0;
    #10;

    // Test case 2
    a = 1;
    #10;


    // Add more test cases as needed

    // End simulation
    $finish;
  end

endmodule

iverilog -o inverter inverter.v tb_inverter.v
vvp inverter
gtkwave waveform.vcd


// full_adder.v
module full_adder (
  input wire a,
  input wire b,
  input wire cin,
  output wire sum,
  output wire cout
);

  assign sum = a ^ b ^ cin;
  assign cout = (a & b) | (b & cin) | (a & cin);

endmodule

// tb_full_adder.v
module tb_full_adder;

  // Inputs
  reg a, b, cin;

  // Outputs
  wire sum, cout;

  // Instantiate the full adder
  full_adder uut (
    .a(a),
    .b(b),
    .cin(cin),
    .sum(sum),
    .cout(cout)
  );

  // Initial block for testbench
  initial begin
    // Open VCD file for waveform dumping
    $dumpfile("waveform_full_adder.vcd");

    // Dump signals to VCD file
    $dumpvars(0, tb_full_adder);

    // Test case 1
    a = 1; b = 1; cin = 0;
    #10;

    // Test case 2
    a = 1; b = 1; cin = 1;
    #10;


    // Add more test cases as needed

    // End simulation
    $finish;
  end

endmodule

![image](https://hackmd.io/_uploads/SygeeC8Ip.png)