# ARM Cortex-A Series Programmer's Guide for ARMv8-A

## Chapter 3 - Fundamentals of ARMv8

Exception levels determine the level of privilege. They are denoted EL*n*, where a higher *n* means higher exeption level.

Typical examples of what runs on the different exeption levels:

**EL0**: Normal user application
**EL1**: OS kernel typically described as *priveleged*
**EL2**: Hypervisor
**EL3**: Low-level firmware, including the Secure Monitor

In general, a piece of software only runs on one EL.

There are two security states, Secure and Non-secure. Virtualization is only provided trough the Non-secure state, or the *Normal world*. That means a hypervisor can only run at EL2 in Normal world. The guest operating systems are unaware that they are sharing time on the system with other guest OS's.

## Execution states

*AArch64*, and *AArch32* are what's called *Execution States*. When in AArch64 state, the processor executes the A64 intruction set.

## Changing Exception levels

Moving to a higher EL indicate increased software execution privilege. An exception cannot be taken to a lower EL. At EL0, there is no exception handling.

When an exception occurs, the program flow is changed. An exception handler starts from a defined vector that relates to the exception taken. Exceptions include:
- Interrupts such as IRQ and FIQ
- Memory system aborts
- Undefined instructions
- System calls
- Secure monitor or hypervisor traps.

The `ERET` instruction ends the exception handling and returns to the previous EL. But, returning from an exception can stay at te same EL or enter a lower EL. It can never move to a higher EL.

# Chapter 4 - ARMv8 Registers

At execution state AArch64 there are 31 x 64-bit GP registers accessibla at all times and in all ELs. These are generally referred to as registers `X0`-`X30`. Each 64-bit register has a 32-bit register `W0`-`W30`, which are the lowest 32 bits of the `x`-register. Reads from `w`-registers disregard the higher 32 bits, and leaves them unchanged. Writes to `w`-registers set the higher bits to zero.

## AArch64 special registers

In addition to the 31 GP-registers there are some special registers:
- Zero register `XZR`/`WZR`
- Program counter `PC`
- Stack pointer (for each EL) `SP_ELn`, where `n` is the EL number
- Program Status Register (for EL1..3) `SPSR_ELn`
- Exception Link Register (for EL1..3) `ELR_ELn`

### Zero register

Writes to the ZR are ignored, and reads return 0.

### Stack pointer

Most instructions cannot reference the SP. However, some forms of arithmetic instructions, such as `ADD`, can read and write to the current SP to adjust it in a function

ADD SP, SP, #0x10 // Adjusts SP to be 0x10 bytes before its current value

### Program counter

The PC is never accessible as a named register. It cannot be specified as the destination of a data processing instruction or a load instruction.

### Exception Link Register

It holds the exception return address

### Saved Process Status Register

The relevant SPSR is used to store the processor state when taking an exception. It holds the `PSTATE` vlue before taking an exception, and is used to return to the same `PSTATE` when done.

It holds flags N, Z, C, V. See figure 4-4 for more info.

## Processor state

The previously referred to `PSTATE` stands for Processor State. It is a collection of fields holding data regarding the state of the processor. Used for returning from exceptions.

## System registers

Controlling the system is done though system registers. They are accessed using `MSR` ans `MRS` instructions.

**AArch64 does not include support for coprocessors.**

The `MSR` and `MRS` instructions may be used as follows:

MRS x0, TTBR0_EL1 // Move TTBR0_EL1 into x0
MSR TTBR0_EL1, x0 // Move x0 into TTBR0_EL1

There is at least one system register for virtualization called `HCR_ELn` and stands for Hypervisor Configuration Register.