# How to use IBEX? ###### tags: `JJLAB-Research` `IBEX-core` `RISC-V` `CPU` ## Simulation Flow ### Build Simulation with Verilator Building simulation binary ``` fusesoc --cores-root=. run --target=sim --setup --build lowrisc:ibex:ibex_simple_system --RV32M=1 --RV32E=0 ``` *lowrisc:ibex:ibexsimplesystem* : the name of core Building software ``` make -C examples/sw/simple_system/hello_test ``` Run Simulation ``` ./build/lowrisc_ibex_ibex_simple_system_0/sim-verilator/Vibex_simple_system --raminit=./examples/sw/simple_system/hello_test/hello_test.vmem ``` ### Build Simulation with VCS Some error may occur in our environment, so we need to modify some parameter to avoid it. first, go into the directory showed below. ``` cd /ibex/ibex/examples/simple_system ``` ``` vim ibex_simple_system.core ``` find out "sim" target, "vcs" tool, and add one line **- '-cflags -std=c++11'** in the vcs_options. ``` sim: <<: *default_target default_tool: verilator tools: vcs: vcs_options: - '-xlrm uniq_prior_final' - '-debug_access+r' - '-cflags -std=c++11' ``` Go back to ibex root directory. ``` cd /ibex/ibex ``` Building simulation binary ``` fusesoc --cores-root=. run --target=sim --tool=vcs --setup --build lowrisc:ibex:ibex_simple_system --RV32E=0 --RV32M=ibex_pkg::RV32MFast --SRAMInitFile=`./examples/sw/simple_system/hello_test/hello_test.vmem` ``` Run Simulation ``` ./build/lowrisc_ibex_ibex_simple_system_0/sim-verilator/Vibex_simple_system --raminit=./examples/sw/simple_system/hello_test/hello_test.vmem ``` ## How to set the design parameter with fusesoc? ``` fusesoc --cores-root=. run --target=sim --setup --build-root ./build/ibex_out lowrisc:ibex:ibex_simple_system --RV32E=0 --ICache=0 --ICacheScramble=0 --ICacheECC=0 --BranchTargetALU=1 --WritebackStage=1 --SecureIbex=0 --BranchPredictor=0 --DbgTriggerEn=0 --PMPEnable=0 --PMPGranularity=0 --PMPNumRegions=4 --MHPMCounterNum=0 --MHPMCounterWidth=40 --RV32M=ibex_pkg::RV32MSingleCycle --RV32B=ibex_pkg::RV32BNone --RegFile=ibex_pkg::RegFileFF ``` ## How to get configured design without verilator compiling? See this link https://github.com/lowRISC/ibex/blob/master/doc/02_user/integration.rst#rtl-file-list ``` fusesoc --cores-root . run --target=lint --setup --build-root ./build/ibex_out lowrisc:ibex:ibex_top ``` ## What is the entrypoint when fusesoc check the design See this link https://fusesoc.readthedocs.io/en/stable/user/overview.html#from-cores-to-a-whole-system-the-build-system