# EasyBuild Tech Talk in AVX10

Fri 13 Oct 2023
09:30-11:00 EDT / 15:30-17:00 CEST

60min + 15min Q&A => announce as 1.5h session

## Title + outline

**AVX10 for HPC, a reasonable solution to the folly of AVX-512**

MMX (via saxpy/daxpy in assembly + assembly/C code to detect instruction set via cpuid)
SIMD vs vector ISAs
use cases: HPC vs the real world
SSE
brief, new registers, etc.
x86_64 after SSE2, more integer/GP registers
ISA vs microarchitecture (C/Fortran compiler analogy)
[question break]
AVX + AVX2
AVX (Sandy Bridge) purely for HPC (16x FLOPS eventually!)
f16c extension (mixed/low precision)
AVX2 (Haswell): 256-bit registers for integer math
AVX-512
(AVX3)
6 levels in AVX-512
good auto-vectorization in compilers
(largely skip Xeon Phi - 7th level)
[question break]
AVX10
incl. what matters from AVX-512
AVX10.n/m (n: revision, m: implementation size)
Grand Rapids => AVX10.1/512
AVX10.n/128 should die
APX
going beyond amd64 (x86_64)

## Demographics

- HPC sysadmins + user support: compiler options, etc.
- RSEs who are writing code

## Questions

- Zoom OK? => yes
- YouTube stream/recording OK => yes
- compiler support
- Intel vs AMD
- Arm SVE
- tool to check which instructions a binary is using (or may be using)?