# Host Bridge to control litex
Reference https://github.com/enjoy-digital/litex/wiki/Use-Host-Bridge-to-control-debug-a-SoC
Reference https://openocd.org/doc/html/Running.html#What-OpenOCD-does-as-it-starts
Pull-request list:
1. https://github.com/enjoy-digital/litex/pull/2150
## Use the barematel test first
### JTAGBone
`python3 -m litex_boards.targets.embedfire_rise_pro --uart-baudrate=921600 --with-jtagbone --cpu-type=vexriscv_smp --cpu-variant=linux --build --load`
`litex_server --jtag --jtag-config openocd_xc7_ft2232.cfg`
manual connect
1. `openocd -f interface/ftdi/digilent-hs2.cfg -f cpld/xilinx-xc7.cfg`
2. `openocd -f prog/openocd_xc7_ft2232.cfg -f stream.cfg -c init; irscan $_CHIPNAME.tap 2; jtagstream_serve $_CHIPNAME.tap 20000; exit`
find the process bin socket `ss -tulnp`
force kill process `kill -9 <PID>` or `pkill -f openocd`
#### Debug openocd cfg file in litex
modiy openocd.py line 125 to
`set rxi [split [drscan $tap {{*}}$txi {endstate}]]`
> first know that `[list {*}…]` is a construct that returns a list of the words in the ellipsis
``` tcl
% set c [list a b]
a b
% set d [list e f]
e f
% set x [list $c {*}$d]
{a b} e f
% set y [lindex $x 2]
f
% set y [lindex $x 1]
e
% set y [lindex $x 0]
a b
```
#### Find out why need to modify?
Florent Kermarrec <florent@enjoy-digital.fr>, 3 years ago (Apr 14, 2022)
openocd/jtag: Add JTAG-UART/JTABBone support to Zynq7000/ZynqMPSoC and define all Xilinx IRs for USERX.
Thanks @smunaut for the initial investigation/implementation. The changes have been minimized to:
Adding an optional delay in TDI: On Zynq devices, TDI is delayed by 1 TCK to bypass the PS tap.
Avoiding OpenOCD's -endstate DRPAUSE on Xilinx that does not seem required.
- [x] Test the openocd version in 2022/4/14 and build the openocd
- [x] v0.12.0-rc1

- [x] is supported `set rxi [split [drscan $tap {{*}}$txi {endstate}] " "]`
- [x] is supported `set rxi [split [drscan $tap {{*}}$txi {endstate}]]`
- [x] v0.12.0-rc2

- [x] is supported `set rxi [split [drscan $tap {{*}}$txi {endstate}] " "]`
- [x] is supported `set rxi [split [drscan $tap {{*}}$txi {endstate}]]`
- [x] v0.12.0-rc3
- [x] is supported `set rxi [split [drscan $tap {{*}}$txi {endstate}] " "]`
- [x] is supported `set rxi [split [drscan $tap {{*}}$txi {endstate}]]`
- [x] v0.12.0
- [x] is supported `set rxi [split [drscan $tap {{*}}$txi {endstate}] " "]`
- [x] is supported `set rxi [split [drscan $tap {{*}}$txi {endstate}]]`
- [x] latest : fd62626dff25cf503a25040d3040b0a2bb9b2a76 (HEAD, tag: latest)
Mon Sep 16 18:01:17 2024 +0300
- [x] is **not** supported `set rxi [split [drscan $tap {{*}}$txi {endstate}] " "]`
- [x] is supported `set rxi [split [drscan $tap {{*}}$txi {endstate}]]`
- [x] Find the which commit change the tcl submodule, latest between v0.12.0 `git log -p -- jimtcl`
- [x] 30c3d077f281876286a7aa37afbd411d4bd1667e
Fri Sep 27 22:40:06 2024 +0200
jimtcl: update to version 0.83
is **not** supported `set rxi [split [drscan $tap {{*}}$txi {endstate}] " "]`
- [x] dccf323c1f78d015f75db4cef8cdc33523e1abd6
Sat Mar 4 12:08:58 2023 +0100
jimtcl: update to version 0.82
is supported `set rxi [split [drscan $tap {{*}}$txi {endstate}] " "]`
#### litex openocd in litex_boards/prog/openocd_xc7_ft2232.cfg
```
interface ftdi
ftdi_vid_pid 0x0403 0x6010
ftdi_channel 0
ftdi_layout_init 0x00e8 0x60eb
reset_config none
source [find cpld/xilinx-xc7.cfg]
source [find cpld/jtagspi.cfg]
adapter_khz 25000
proc fpga_program {} {
global _CHIPNAME
xc7_program $_CHIPNAME.tap
}
```
#### use lsusb to check the product id
```
idVendor 0x0403 Future Technology Devices International, Ltd
idProduct 0x6010 FT2232C/D/H Dual UART/FIFO IC
bcdDevice 7.00
iManufacturer 1 Digilent
iProduct 2 Digilent Adept USB Device
```
#### openocd dir
/usr/local/share/openocd/scripts
### UARTBone (Successful)
`python3 -m litex_boards.targets.embedfire_rise_pro --uart-baudrate=921600 --uart-name=crossover --with-uartbone --cpu-type=vexriscv_smp --cpu-variant=linux --build --flash --load`
`litex_server --uart --uart-port=/dev/usbSerial --uart-baudrate=921600`
```
cd build/embedfire_rise_pro
litex_term crossover
```