# ECO with Behavioral Change Guidance
ICCAD 2021 Problem A
- [ ] Registration deadline 2021/05/10 17:00:00 (GTM+8)
- [ ] Alpha test submission 2021/06/05 17:00:00 (GTM+8)
- [ ] Beta test submission 2021/07/24 17:00:00 (GTM+8)
- [ ] Final submission 2021/08/30 17:00:00 (GTM+8)
- [ ] Award ceremony 2021/11/1

## Reference
1. A Robust Functional ECO Engine by SAT Proof Minimization and Interpolation Techniques 2010
2. Interpolation-Based Incremental ECO Synthesis for Multi-Error Logic Rectification 2011
3. Multi-Patch Generation for Multi-Error Logic Rectification by Interpolation with Cofactor Reduction 2012
4. Match and replace: A functional ECO engine for multierror circuit rectification 2013
5. Semi Formal ECO Method 2018
6. Efficient Computation of ECO Patch Functions 2018
7. tool :https://github.com/YosysHQ/yosys
8. Incremental Synthesis 1994

## Testcase Generation Phase
### Input
- number of gate, level, po and pi
- number of gate rewiring, inverter insertion and gate type change
### Output
- R1.v
The original specification
- R2.v
The new specification
- G1.v
The implementation netlist synthesized and optimized from R1

### Todo
- [ ] Find tool to optimize R1 to G1 (ABC, design compiler...)

## Parsing Phase @DhgirAbien
### Input
- The netlist of R1, R2 and G1
- 

### Output
- circuit-based data structure for simulation and SAT
### Todo
- [ ] To Implement verilog LL(1) parser

## Matching Phase
- Fig. 1
- Fig. 2

### Input
- The circuit-based data structure of R1, R2 and G1
### Output
- The output & input cut (R1, R2)
### Todo

seNet_r1r2 = find_structure_equivalent_net_pair(R1, R2);
feNet_r1r2 = find_functional_equivalence_net_pair(R1, R2);
feNet_r1g1 = find_functional_equivalence_net_pair(R1, G1);

inputCut = PImatch(feNet_r1r2, feNet_r1g1);
outputCut = POmatch(seNet_r1r2, feNet_r1g1);

## Refactoring & Replacing Phase
### Input
- The set of rectification pairs of (G1, R2)
### Output
- The netlist of patch
### Todo

rp_with_cost_set = reuse_internal_node(G1, rp_pair)
patch = rp_pair_selection(rp_with_cost_set, R1, G1)
patch_verilog = patch_gen(patch)

## Verifying Phase
### Input
- The netlist of R2 ,G1 and Patch
### Output
- EQ or NEQ
- Cost of the patch
### Todo
- Apply patch and calculate cost
- Use ABC cec command to check