---
# System prepended metadata

title: SoC Laboratory Assignment W5
tags: [Assignment, SoC Laboratory]

---

# SoC Laboratory Assignment W5

> [TOC]

## 1. RTL-synthesis consistency

#### a) Evaluate the blocking and non-blocking assignment

1. Yes, both circuits produce the same combinational logic.
2. However, the behaviors of the circuits are different in simulation. For the final Y value:
    * Circuit A: y = (x_prev | c) = (0 | 0) = 0
    * Circuit B: y = (a & b) | c = 1

---

#### b) What is the logic/gate generated from the code4a, and code4b

In the Code4a, the synthesizer will generate the logic following `case` behavior.
```
y[0] = en & ~a[1] & ~a[0];
y[1] = en & ~a[1] &  a[0];
y[2] = en &  a[1] & ~a[0];
y[3] = en &  a[1] &  a[0];
```

In the Code4b, `case` is declared with `full_case`. the unspecified states (`en`) will be treated as don't care.
```
y[0] = ~a[1]&  ~a[0];
y[1] = ~a[1] &  a[0];
y[2] =  a[1] & ~a[0];
y[3] =  a[1] &  a[0];
```
---

#### c) What is logic/gate generated from code5a, and code5b ?

In the code5a, the states in `case` have priority. only one state can be excuted.
```
z =       a & b ;
y = ~z & (c & d);
```


In the code5b, every state in `case` run parallelly. `case` can be interpreted as
```
z = a & b;
y = c & d;
```

---

## 2. Construct design

#### d) Design an axi-stream interface with SRAM (1T read latency) to achieve 1-1-1 back-to-back data transfer
1. Draw Waveform of `tvalid`, `tready`, `tdata`, `muxsel`, `ffen`, `addr`, `rdata`, `tdata`

![pf](https://hackmd.io/_uploads/rJv8CKU2ye.png)

2. Write the Verilog code

```
module AXIS #(
    parameter DATA_WIDTH = 32,
    parameter ADDR_WIDTH = 32
)(
    input                   clk,
    input                   rst_n,
    input                   tready,
    output                  tvalid,
    output [DATA_WIDTH-1:0] tdata
);
    reg  [ADDR_WIDTH-1:0] addr;
    wire [DATA_WIDTH-1:0] sramd;
    reg  [DATA_WIDTH-1:0] ff;
    reg                   muxsel_ffen; // mulsel & ffen share the same logic
    
    
    assign tvalid = (addr != 0);
    assign tdata = (muxsel_ffen) ? sramd : ff;
    
    SRAM sram(.clk(clk), .en(rst_n), .addr(addr), .dout(sramd));
    
    // addr
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            addr <= 0; 
        end else begin
            if (addr == 0) addr <= 1;
            else addr <= (tready) ? addr + 1 : addr;
        end
    end
    
    // ff
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            ff <= 0; 
        end else begin
            if (muxsel_ffen) ff <= sramd;
        end
    end
    
    // muxsel & ffen
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) muxsel_ffen <= 0; 
        else muxsel_ffen <= (addr == 0) ? 1 : tready;
    end
    
endmodule
```

3. Run the simulation
![wave](https://hackmd.io/_uploads/BJUQ7rF21g.png)

---

## 3. FSM

#### e) Refer to the timing waveform, is it a Moore or Mealy Machine?

Moore Machine. It has synchronous output.

---

## 4. SRAM

#### f) In ASIC flow, How to write verilog code to create SRAM?

If systhesizing the code in DC, the result will get a bunch of registers.
The SRAM should be defined as macro, and the `.v` files pervided by vender include the timing information for simulation.

---

## 5. Reset

#### g) Select the Verilog code, Waveform, Schematic for Synchronous/Asynchronous Reset

| Reset Type         | Verilog | Waveform | Schematic |
|--------------------|---------|----------|-----------|
| Synchronous Reset  | A       | B        | B         |
| Asynchronous Reset | B       | A        | A         |