# SoC Laboratory Assignment W3

## 1. AXI

#### a) Design the interface logic between AXI and SRAM using minimum hardware resource, and draw timing waveform

For write operation, the SRAM starts writing after both `awvalid` and `wvalid` are asserted, and returns `awready` and `wvalid` next cycle.
For read operation, the SRAM should first receive both `arvalid` and `rready`, and returns the `rdata` and `rvalid` with one cycle delay.
When AXI receives read and write requests at the same times, it will process the read operation first.



#### b) Interleave order: axi burst type = interleave order, the starting address is 011, what is address sequence for data access?

[3, 2, 1, 0, 7, 6, 5, 4]

#### c) How to handle different access order from CPU and IO

CPU cache and DRAM use interleave order, while IO uses linear order. Therefore, the interleave sequence should start at 0, performing as linear order.

## 2. IO cache

#### d) TPH Implementation options

<table>
<thead>
<tr>
<th>Read/Write</th>
<th>Operations</th>
<th>TPH=00<br>Bi-directal structure</th>
<th>TPH=01<br>Requester</th>
<th>TPH=10<br>Target</th>
<th>TPH=11<br>Target with priority</th>
</tr>
</thead>
<tbody>
<tr>
<td rowspan=3>IO Read</td>
<td>Speculate read DRAM</td>
<td></td>
<td>✅</td>
<td></td>
<td></td>
</tr>
<tr>
<td>Cache hit & dirty,<br>
write and invalidate?</td>
<td>✅</td>
<td></td>
<td></td>
<td></td>
</tr>
<tr>
<td>Cache hit & not dirty,<br>
cache supply data</td>
<td></td>
<td></td>
<td>✅</td>
<td></td>
</tr>
<tr>
<td rowspan=3>IO Write</td>
<td>Invalidate cache</td>
<td></td>
<td>✅</td>
<td></td>
<td></td>
</tr>
<tr>
<td>Write update cache</td>
<td>✅</td>
<td></td>
<td></td>
<td></td>
</tr>
<tr>
<td>Write allocate cache</td>
<td></td>
<td></td>
<td></td>
<td>✅</td>
</tr>
</tbody>
</table>