# SoC Laboratory Assignment W7

#### a) The example shows RAW dependency. Explain the software and hardware techniques to solve the problem.

I0: LDR X1, [X2]
I1: ADD X1, X1, X3 // X1 RAW
I2: LDR X3, X2, #4
I3: SUB X2, X3, #1 // X3 RAW

Software technique: compiler inserting NOP
Hardware techniques: dynamic pipeline, instruction reordering, data forwarding

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#### b) Identify the load-to-use harzards? And reorder the instruction to eliminate it.

Original order:

I0: LW  R1, b
I1: LW  R2, e
I2: ADD R3, R1, R2 // R2 load-to-use
I3: SW  R3, a
I4: LW  R4, f
I5: ADD R5, R1, R4 // R4 load-to-use
I6: SW  R5, c

After reorder:

I0: LW  R1, b
I1: LW  R2, e
I4: LW  R4, f      // program I4 first
I2: ADD R3, R1, R2 // R2 from I1 WB forwarding
I3: SW  R3, a
I5: ADD R5, R1, R4 // no load-to-use
I6: SW  R5, c

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#### c) Identify RAW, WAW, WAR dependency. Use Register renaming to eliminate WAW, WAR dependency

##### RAW:
* I0 & I1 r1
* I1 & I2 r3
* I2 & I3 r1
* I1 & I3 r3

##### WAW:
* I0 & I2 r1

##### WAR:
* I1 & I2 r1
* I0 & I3 r2
* I1 & I3 r2
* I2 & I3 r2
* I1 & I3 r3

<table>
<thead>
<tr>
<th>Instructions</th>
<th colspan=3>Map table</th>
</tr>
</thead>
<tbody>
<tr>
<td></td>
<td>r1</td>
<td>r2</td>
<td>r3</td>
</tr>
<tr>
<td></td>
<td>11</td>
<td>12</td>
<td>13</td>
</tr>
<tr>
<td>I0: add r1, r2, r3</td>
<td>11</td>
<td>12</td>
<td>13</td>
</tr>
<tr>
<td>I1: sub r3, r2, r1</td>
<td>11</td>
<td>12</td>
<td>14</td>
</tr>
<tr>
<td>I2: mul r1, r2, r3</td>
<td>15</td>
<td>12</td>
<td>14</td>
</tr>
<tr>
<td>I3: div r2, r1, r3</td>
<td>15</td>
<td>16</td>
<td>14</td>
</tr>
</tbody>
</table>

| Original instructions | Renamed Instructions |
|-----------------------|---------------------|
| add r1, r2, r3 | add pr11, pr12, pr13 |
| sub r3, r2, r1 | sub pr14, pr12, pr11 |
| mul r1, r2, r3 | mul pr15, pr12, pr14 |
| div r2, r1, r3 | div pr16, pr15, pr14 |