# SoC Laboratory Assignment W4

## 1. Testbench

#### a) Do the two always block behave the same?

No. Nonblocking statements (with dependency) in different sequences will cause different simulation results.

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#### b) Which of the following code snippets is race free

A is race free.
B initializes `clk` with `0` and `1` at the same time.
C passes the values `2` and `9` to `x` in different `always` blocks simultaneously.
D cannot determine the sequence of two processes.

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## 2. Delay

#### c) Draw the Timing Waveform for the 3 cases

* A
* B & C

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## 3. Blocking/nonblocking

#### d) Asynchronous and synchronous reset at time zero

1. Asynchronous reset
* clock_1_nonblocking
* reset_blocking
2. Synchronous reset
* clock_1
* reset_nonblocking

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#### e) Rewrite the Testbench code to generate the desired rdata sequence

// Test bench
task tx;
    input value;
    begin
        data <= value;
        @(posedge clk);
    end
endtask

tx(8'h05);
tx(8'h06);
tx(8'h07);