# SoC Laboratory Assignment W2

## Basic Coding Style

### Rewrite the code to meet coding style

1. begin-end

if (condition) begin
  foo = bar;
end else begin
  foo = num;
end

2. Space in expression

assign a = ((addr & mask) == My_addr) ? b[1] : ~b[0];

3. Space in array dimension declaration - 1

logic [7:0][3:0] data[128][2];

4. Space in array dimension declaration - 2

typedef logic [31:0] word_t;

5. Parentheses

assign foo = condition_a ? (condition_a_x ? x : y) : b;

### Instantiate a module with redefined parameters

Module definition

module myreg(q, d, clk, rst_n);
  parameter Trst = 1,
            Tckq = 1,
            SIZE = 4,
            VERSION = "1.1";

  output [SIZE-1:0] q;
  input  [SIZE-1:0] d;
  input             clk, rst_n;

  reg    [SIZE-1:0] q;
  
  always @(posedge clk or negedge rest_n)
    if (!rst_n) q <= #Trst 0;
    else        q <= #Tckq d;
endmodule

Instantiate myreg with parameters redefined as `SIZE` = 8, `Tckq` = 2

module name (q, d, clk, rst_n);
  output [7:0] q;
  input  [7:0] d;
  input        clk, rst_n;
  
  myreg #(
    .SIZE(8),
    .Tckq(2))
  r1 (
    .q(q),
    .d(d),
    .clk(clk),
    .rst_n(rst_n)
  );
endmodule

## Logic Design Basics

### Avoid using latches

\#1
In default statement, `q` maintains state by holding a value. Using `assign` can aviod latch being generated

assign q = !c ? 1'b1 : 1'b0;
assign z = !c ? 1'b0 : z;

\#2
`s` signal is not completely assigned in all conditions of `case`. To remove the latch, the default value is added before `case`.

always @* begin
  // aviod latch
  z = 1'b0;
  s = 1'b0;
  case (d)
    2'b00:  z = 1'b1;
    2'b01:  z = 1'b0;
    2'b10: begin
            z = 1'b1;
            s = 1'b1;
    end
    defalut: begin
            z = 1'b0;
            s = 1'b0;
    end
  endcase
end

### Fix design timing using time borrowing techniques


The second FF should be replaced by a negative-triggered latch (L2). Upon receiving data from FF1, L2 immediately passes it to the next combination logic. The Path#2 can borrow time from the preceding cycle, enabling the circuit to meet the timing requirement.