# 描述電路的三種層次
###### tags: `verilog` `digital design` `邏輯設計` `邏設`

[TOC]

## Structure Description ( Structural Modeling )

Format：

<gate> name ( output, intput1, input2,... );

- Also called `Gate Level`
- tlts;dr : build a circuit of primitive gates.

|Gate Name|Icon|Example|Info|
| --- | --- | --- | --- |
| NOT |  | not not1( B, A ); | B = ~A |
| AND |  | and and1( C, A, B ); | C = A & B |
| OR |  | or or1( C, A, B ); | C = A \| B |
| XOR |  | xor xor1( C, A, B ); | C = A ^ B |

Example：

<div style="text-align: center" >
<img src="https://i.imgur.com/Nkh9Ij7.png" height="400" width="500"/>
</div>

module comparator( A, B, gt, lt, eq );
    input A, B;
    output gt, lt, eq;
    
    wire negA, negB;
    
    not not1( negA, A );
    not not2( negB, B );
    and and1( gt, A, negB );
    and and2( lt, negA, B );
    xnor xnor1( eq, A, B );
    
endmodule

## Dataflow Description ( Dataflow Modeling )

Format：

wire A;
assign A = 1'b0;

//Note!! assign statement have to be used with wire type 

* Assign statment is also called continuous assignment.

* Once the value changes, the assign statement will be driven.

* Assign statement can be used with `wire`, <font color=#bf2222>which means you can't assgin a value to an `reg`</font>.

* `assign a = a + b` is <font color=#bf2222>not allowed</font>. A `wire` can't be assigned with a value which is related to itself.

* Multiple assignment is not allowed. For exmaple:

assign a = b; 
assign a = c;  // Error

* Advance Usage:

assign a = { 1'b0, 1'b1 };  // a = 2'b01
assign a = { 2{2'b10} };    // a = 4'b1010

- Comparator example (the circuit is same as the Example circuit in Gate Level paragraph.)

module comparator( A, B, gt, lt, eq );
    input A, B;
    output gt, lt, eq;
    
    assign gt = A & ~B;
    assign lt = ~A & B;
    assign eq = ~( A ^ B );
    
endmodule

More infomation, please refer to [Lexical Conventions](https://hackmd.io/s/r1v7PDeYl)。

## Behavior Description ( Behavior Modeling )

- Format :

initial begin
    ...
end

always @( sensitivity list ) begin
    ...
end

- It is also called `procedural assignment`. Means that it will be driven under some condition.

- We call such code structure a `block`, so it is also called `block assignment`

- You can only assgin a value to a `reg` in `block statement`.

- Two different assginments : `initial block` 和 `always block`。

1. <font color = #1644aa>initial block</font>：
- Only used in testbench.
- The block is driven one time in a process.
- It can be synthesized to a circuit.

2. <font color = #1644aa>always block</font>：
- The block will be driven once one of the values in sensitivity list changes.
- `Sensitivity list` usually replaced by `*`. <font color=#bf2222>it means once a value changes, the block will be driven.</font>

module comparator( A, B, gt, lt, eq );
    input A, B;
    output gt, lt, eq;
    
    always @(*) begin
        gt = A & ~B;
        lt = ~A & B;
        eq = ~( A ^ B );
    end
    
endmodule

<font color=#bf2222>We will teach you more Verilog skill in advanced in Lab 2 and Lab 3.</font> But if you are insterested in Verilog, You can see more infomation on [Verilog HDL 教學講義](https://hom-wang.gitbooks.io/verilog-hdl/content/index.html)

# [:maple_leaf:Homepage:maple_leaf:](https://hackmd.io/s/ByZ-fyuHV)