2020 Logice Design Exam2
===
###### tags: `verilog` `邏輯設計` `邏設` `digital design`
1. Suppose `A` is a 4-bit binary number declared with type wire. How can we assign a value of 3 to it? Please write down the code fragment. (2pts)
2. Suppose `B` is a 4-bit binary number declared with type reg. How can we assign a value of 3 to it? Please write down the code fragment. (2pts)
3. What is the difference between `!` and `~` ? Please explain it with an example.(2pts)
4. What is the function of the following code.(Hint. Why should we add the following code in a testbench?) (3pts)
```verilog=
module tb();
initial begin
$fsdbDumpfile("as4.fsdb");
$fsdbDumpvars;
end
//...
endmodule
```
5. Describe the following circuit in Verilog. (3pts)

```verilog=
module comparator( A, B, gt, lt, eq );
input A, B;
output gt, lt, eq;
wire negA, negB;
assign negA = ~A;
assign negB = ~B;
assign gt = ...;
assign lt = ...;
assign eq = ...;
endmodule
```