# SCLD <!-- - [交電共同網頁](https://sites.google.com/access.ee.ntu.edu.tw/scld-2019-fall/) --> - [Chap 11 Latches and Flip-flops](/s2qpPbl2QLe8pRo71gG5Cg) - [Chap 12 Registers and Counters](/8eb5wN-DRMSlXscMArBhsg) - [Chap 13 Analysis of Clocked Sequential Circuits](/80UWJzSeQgitwy7xeCcaMg) - [Chap 14 Derivation of State Graphs and Tables](/LXOP-VITQvud6TBSDE25uA) - [Chap 15 Reduction of State Tables State Assignment](/96dmXAHcRlee18z2vBCadQ) - [Chap 16 Sequential Circuit Design](/WsXJ_UgMRZSYFfIHH3HlbA) - [考古題](/Hy9yrd4gU)
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