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###### tags: `SCLD`
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# Chap 14 Derivation of State Graphs and Tables

## 14.1 Design of a Sequence Detector
example:
design the circuit so that any input sequence ending in 101 will produce an output Z = 1
coincident with the last 1
*the symbol before the slash is the input and the symbol after the slash is the corresponding output*

#### Mealy machine
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<img src="https://i.imgur.com/ZW6bi06.png" height="160">

target: S~0~S~1~S~2~ = 101
S~0~: get 1 →store it ; get 0 → again

S~0~ S~1~ S~2~ 基本上可以隨便代
(i.e. S~0~ 可以 00 or 01 or whatever 代替)
出來的電路、SOP 會不一樣，但實質結果是相同的

#### Moore machine
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<!-- Mealy: output 跟著弧線
Moore: output 不在弧線上， so S~2~=1 時不可回到 S~1~(whose output is 0) 如 Mealy -->


initial state = 1
→ ++01++000 underline part Z=1

## 14.2 More Complex Design Problems
#### a Mealy example
The output Z should be 1 if the input sequence ends in either 010 or 1001, and Z should be 0 otherwise.

010|
_10|01

1001|
__ 01|0

"|": 接在一起處
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#### a Moore example
The output Z is to be 1 if the total number of 1’s received is ++odd++ and at least ++two consecutive 0s++ have been received.
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## 14.3 Guidelines for Construction of State Graphs
The circuit examines groups of four consecutive inputs and produces an output Z = 1 if the input sequence 0101 or 1001 occurs. The circuit resets after every four inputs.
【Mealy】
0101 & 1001 可共用
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錯的 → 進到紅框區 → output 0
a group of 5 → 下面再多一層 以此類推

==跳過 example 2, 3==

## 14.4 Serial Data Code Conversion
NRZ：non return to zero, 不變
RZ：return to 0, 變 1 後, 後半變回 0
NRZI：inverted, 看 1 的奇偶 (i.e. 0 → Q^+^=Q ; 1 → Q^+^=Q')
Manchester：0 → 後半變 1 ; 1 → 後半變 0

#### Mealy ver.
NRZ {→|convert} Manchester

ideal：忽略延遲
actual：有延遲，出現 false output
<!-- clock2 頻率 2 倍 for manchester -->
clock2 頻率 2 倍 → 所有 output changes 都在 edge 上
NRZ stable for 2 clock2 period
clock change but input hasn't → glitch

S~1~ 完不會有 1 so －

#### Moore ver.
NRZ {→|convert} Manchester

## 14.5 Alphanumeric State Graph Notation
(a) F → forward ; R → reverse
(b) 考量到 FR=11,00

從 S~0~ 發出的線
3 條線 or 在一起，為 1 → 至少一條為 1
`F + F′R + F′R′ = F + F′ = 1`
3 條線兩兩 and 在一起，皆為 0 → 小於 2 條為 1
`F·F′R = 0, F·F′R′ = 0, F′R·F′R′ = 0`
→ 恰好 1 條為 1

for Mealy：
X~i~X~j~/Z~p~Z~q~ means if X~i~X~j~ = 11 (other Xs don't care), Z~p~Z~q~ = 11 (others Zs = 0)
e.g. X1X4′/Z2Z3 means 1--0/0110

## 14.6 Incompletely Specified State Tables
#### BCD (0~9 in binary i.e. 0000-1001)
while in last bit:
if 1s = even → 1
else → 0

#### 101 disjoint, output only used in the end

## Problems
#### 14.16
ans

#### 14.31
ans

#### 14.33
ans

#### 14.38
ans

#### 14.43
ans

#### 14.45
ans