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###### tags: `SCLD`
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# Chap 13 Analysis of Clocked Sequential Circuits
## 13.1 A Sequential Parity Checker
奇數個 1 → 1
偶數個 1 → 0
出錯 → 0→1 or 1→0 → parity 改變 → 知道出錯

累積 input 偶數 → Z=0
累積 input 奇數 → Z=1
![]()
<img src="https://i.imgur.com/U4CjJrZ.png" height="120">

## 13.2 Analysis by Signal Tracing and Timing Charts
The state graph for a <font color="#F2492B">Moore machine</font> has the output associated with the state (as in Figures 13-3 and 13-9). If the output is a function of both the present state and the input (as in Figure 13-7), the circuit is referred to as a <font color="#F2492B">Mealy machine</font>.
### Moore machine
Z=(0): 跟 X 沒關係
>the output which results from application of a given input does not appear until after the active clock edge
>
### Mealy Machine
>The input is synchronized with the clock so that input changes occur after the falling edge.

>The output depends on both the input (X) and the flip-flop states (A and B), so Z may change either when the input changes or when the flip-flops.
change state.

Z=(0/1):短暫對到舊的

input stable, flip-flop change state → may have false output

## 13.3 State Tables and Graphs
### steps
1. input & output equations
2. next-state equation
3. next-state map
4. trantition table

### Moore Transition (for figure 13-5)
1. input equations and output equation
- D_A = X ⊕ B′
- D_B = X + Α
- Z = A ⊕ B

2. next state equation
- A⁺ = X ⊕ B′
- B⁺ = X + A

3. map

4. moore state table
<img src="https://i.imgur.com/k65cCo4.png" height="120">
<img src="https://i.imgur.com/tO3DnGs.png" height="130">

<!-- 左側(紅框)為 A⁺，右側為 B⁺
(對照上圖) -->

4. moore state gragh

### Mealy Transition (for figure 13-7)
1. next-state and output equations
A⁺ = J_AA′ + K_A ′A = XBA′ + X′A
B⁺ = J_BB′ + K_B ′B = XB′ + (AX)′B = XB′ + X′B + A′B
Z = X′A′B + XB′ + XA
2. next-state and output maps
3. mealy state table
4. mealy state gragh

### serial adder
Q⁺ = C_i+1
只有 C_i+1 被 clock 擋下


(rising)

state gragh
mealy machine, 1 flip-flop, 2 states

Mealy sequential circuit with two inputs
and two outputs
corresponding state graph

### timimg charts
clock 跳之前就讀取，但 clock 跳的時候才 update

## 13.4 General Models for Sequential Circuits

t~clk~ (min) = t~p~ + t~c~ + t~su~
t~clk~ (min) = t~x~ + t~c~ + t~su~
t~clk~ (min) = t~p~ + t~c~ + t~su~ + t~sk~

<大概知道就好>
t~p~ + t~c~ ≥ t~sk~ + t~h~
t~p~ ≥ t~sk~ + t~h~
</大概知道就好>



X~1~X~2~=00 → X=0, and so on and so forth
S^+^ = δ(S, X) ; Z = λ(S, X)
根據上表得出
δ(S~0~, 1) = S~2~ ; δ(S~2~, 3) = S~1~ ; λ(S~0~, 1) = 2 ; λ(S~2~, 3) = 1

## Problems
#### 13.7
ans

#### 13.17
ans

#### 13.20
ans

#### 13.23
ans

#### 13.25
ans