---
###### tags: `SCLD`
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# Chap 16 Sequential Circuit Design
## 16.2
BCD to excess-3
excess-3：+3
0-9 → 3-12
e.g. t~2~ 01 X=1 → 101 (補在左邊) 去對上表 BCD，對應到同列 Z 的 t~2~ → Z = 0
<!-- handsomejingyuan -->
<!-- {黃靖元|大帥哥} -->
assign 值時 (for the purpose of 比較好圈)：
- previous state 一樣的放在一起
(e.g. H&M 在一起)
- output 一樣的放在一起

<!-- FIGURE 16-2 -->
<!-- FIGURE 16-3 Karnaugh Maps for Code Converter Design -->
<!-- FIGURE 16-4 Code Converter Circuit -->

## 16.3 Design of Iterative Circuits
<!-- FIGURE 16-5 Unilateral Iterative Circuit -->
<!-- FIGURE 16-6 Form of Iterative Circuit for Comparing Binary Numbers -->
each compare x~i~&y~i~ then pass result to right

<!-- TABLE 16-4 State Table for Comparator -->
只有一個是 1 (?)

a~2~ = a1 + x~1~′y~1~b~1~′ = x~1~′y~1~
b~2~ = b~1~ + x~1~y~1~′a~1~′ = x~1~y~1~
<!-- table 16-5 -->
<!-- fig 16-7 -->
<!-- fig 16-8 -->
<!-- fig 16-9 -->

output 只跟 state 有關 → Moore

## 16.4 Design of Sequential Circuits Using ROMs and PLAs
### ROM
<!-- table 16-6 -->
111: all x
<img src="https://i.imgur.com/eFb2mQp.png" height="340">
<!--  -->
<!-- FIGURE 16-10 Realization of Table 16-6(a) Using a ROM -->

### PLA
from figure 16-3
D~1~ = Q~1~^+^ = Q~2~′
D~2~ = Q~2~^+^ = Q~1~
D~3~ = Q~3~^+^ = Q~1~Q~2~Q~3~ + X′Q~1~Q~3~′ + XQ~1~′Q~2~′
Z = X′Q~3~′ + XQ~3~
<!-- TABLE 16-7 -->
Q^+^ = D = A′BQ′ + AB′Q
<!-- FIGURE 16-11 Segment of a Sequential PAL -->

## Problems
### 16.17
:::spoiler ans
:::

### 16.22
:::spoiler ans
:::

### 16.29 (a)(b)
::: spoiler ans
:::

### 16.34
::: spoiler ans
:::

https://drive.google.com/file/d/1gU2oCa33dcbJla--n3FkUJmQ4rTN1y6Q/view