---
# System prepended metadata

title: Chap 12 Registers and Counters
tags: [College Notes, SCLD]

---

---
###### tags: `College Notes`,`SCLD`
---
# Chap 12 Registers and Counters
## 12.1 Registers and Register Transfers
![](https://i.imgur.com/UdHJzNd.png) (falling-edge)
Load = 0 → register not clocked → stable  
Load = 1 → clock → flip-flop  
if Load = 1 and falling edge, Q=0000→1101

![](https://i.imgur.com/UwyhHTH.png)
better, no timing problem (因為直接接)

bus
<img src="https://i.imgur.com/QrRf0J5.png" height="200">

### Data Transfer Between Registers
- E~n~=1 → Register A enabled
- E~n~=0 → Register B enabled

for D<sub>1</sub>: En=1 → D<sub>1</sub>=A<sub>1</sub>, En=0 → D<sub>1</sub>=B<sub>1</sub>
for D<sub>2</sub> 同理
![](https://i.imgur.com/YnKsOdI.png)

enabled when En=0
![](https://i.imgur.com/YP3hvQq.png)

EnA=0 → A enabled
LdG=1 → load into G
![](https://i.imgur.com/M0m4LEo.png)
EF=00 → A
EF=01 → B
EF=10 → C
EF=11 → D

### accumulator
sum 輸出到 D 被 flip-flop 擋住, clock edge 時再 pass to Q 加回去 (:arrow_right:  累加)  
→ 讓大家同時進行累加
![](https://i.imgur.com/ekzV2h8.png)

**adder cell with multiplexer**
Ld(Load) = 0 → 同上圖的 FA  
Ld = 1 → 初始值
![](https://i.imgur.com/b8jPHGW.png)

## 12.2 Shift Registers
shift=1 → data right shift
![](https://i.imgur.com/SMfXbri.png)
clock=0→1 → SI pass to Q<sub>3</sub>, Q<sub>3</sub> pass to Q<sub>2</sub>, .....
(if 虛線 connects → end around shift)

![](https://i.imgur.com/LGuB7FB.png)
SI=1,1,0,1
Q[3..0]=0101→1010→1101→0110→1011


8-bit shift register
![](https://i.imgur.com/iM5r2w3.png)
![](https://i.imgur.com/CgFDCJN.png)
[SR flip-flop](https://hackmd.io/s2qpPbl2QLe8pRo71gG5Cg?view#115-S-R-Flip-Flop):
```
SR=00 → no change
SR=01 → Q=0
SR=10 → Q=1
SR=11 → not allowed
```
今 S=SI, R=SI'
so 每個都變 D flip-flop

shifts in {→| 7 clock periods later}shifts out
![](https://i.imgur.com/nnSGhbm.png)

can all 4 bits can be loaded in & read out simultaneousely
![](https://i.imgur.com/K5k0d7i.png)
<!-- Sh=1 → everone shifts right
Sh=0, L=1 → D loaded
Sh=0, L=0 → no change -->
![](https://i.imgur.com/hIVKvmh.png)

![](https://i.imgur.com/rKFtwqw.png)
Q<sub>3</sub><sup>+</sup> = Sh′ · L′ · Q<sub>3</sub> + Sh′ · L · D<sub>3</sub> + Sh · SI
Q<sub>2</sub><sup>+</sup> = Sh′ · L′ · Q<sub>2</sub> + Sh′ · L · D<sub>2</sub> + Sh · Q<sub>3</sub>
Q<sub>1</sub><sup>+</sup> = Sh′ · L′ · Q<sub>1</sub> + Sh′ · L · D<sub>1</sub> + Sh · Q<sub>2</sub>
Q<sub>0</sub><sup>+</sup> = Sh′ · L′ · Q<sub>0</sub> + Sh′ · L · D<sub>0</sub> + Sh · Q<sub>1</sub>

timing diagram when SI=0 and D[3..0]=1011
(falling edge)
![](https://i.imgur.com/1KgGehC.png)

### 3-bit shift register with inverted feedback
![](https://i.imgur.com/JP1inFw.png)
00{++0++|→1 & 左插} → 10++0++ → 110 → ...
![](https://i.imgur.com/bAhx21h.png)
circuit that cycles → counter

<!-- 似乎沒教 -->
<!-- general shift register counter
![](https://i.imgur.com/YNkZESR.png) -->

## 12.3 Design of Binary Counters
#### use T flip-flops
T flip-flop: Q<sup>+</sup>=T⊕Q[<sup>[1]</sup>](https://hackmd.io/s2qpPbl2QLe8pRo71gG5Cg?both#117-T-Flip-Flop "Chap 11 - T flip-flop")
![](https://i.imgur.com/lscRaRC.png)
C只有在 A=B=1 時會進位 so T~C~=AB
<!-- CBA=000 → 001 (bc T<sub>A</sub>=1) → 010 :arrow_down:  -->
C^+^ = C ⊕ T~C~ so：
C != C^+^ 代表 T~C~ = 1
C = C^+^ 代表 T~C~ = 0
:arrow_double_down: 
![](https://i.imgur.com/Qr9ERQY.png)

T~C~=AB
T~B~=A
T~A~=1
![K Map](https://i.imgur.com/H5sdlY5.png)

#### 以 D flip-flop 取代 T flip-flop
(等效)
![](https://i.imgur.com/Xxlcf7I.png)
D<sub>A</sub> = A<sup>+</sup> = A ⊕ 1 = A'
D<sub>B</sub> = B<sup>+</sup> = B ⊕ A
D<sub>C</sub> = C<sup>+</sup> = C ⊕ BA
![](https://i.imgur.com/vdnbvWP.png)


### up-down binary counter
D<sub>A</sub> = A<sup>+</sup> = A ⊕ (U + D) (A~U~ = A~D~)
D<sub>B</sub> = B<sup>+</sup> = B ⊕ (UA + DA′) (B~U~ = B~D~')
D<sub>C</sub> = C<sup>+</sup> = C ⊕ (UBA + DB′A′) (B~U~A~U~ = (B~D~A~D~)')
![](https://i.imgur.com/u8cjxfE.png)
use D flip-flops
![](https://i.imgur.com/3dQQjhW.png)

### laodable counter with clock enable
<img src="https://i.imgur.com/3D6l3nl.png" height="150">

![](https://i.imgur.com/GBLOW71.png)
Ct(count)=1 → next state ([original bianary counter](#以-D-flip-flop-取代-T-flip-flop))
Ld=1(→Ld'=0) → D go through XOR
<!-- ![](https://i.imgur.com/AD2pSdR.png) -->
![](https://i.imgur.com/ZPO6uIR.png)

A<sup>+</sup> = D<sub>A</sub> = (Ld′·A + Ld ·D<sub>Ain</sub>) ⊕ Ld′·Ct
B<sup>+</sup> = D<sub>B</sub> = (Ld′·B + Ld ·D<sub>Bin</sub>) ⊕ Ld′·Ct · A
C<sup>+</sup> = D<sub>C</sub> = (Ld′·C + Ld ·D<sub>Cin</sub>) ⊕ Ld′·Ct · B · A

## 12.4 Counters for Other Sequences
### T flip-flop iplementation
---
假設有一個東西的 transition map 長這樣
![](https://i.imgur.com/dmsKIy4.png)
可根據這個 map 反向做出他的 circuit

畫出 transition table
![](https://i.imgur.com/hSGSLKB.png)
根據上表填出 next-state map
![](https://i.imgur.com/SAo9MNh.png)

---

for [T flip-flop](https://hackmd.io/s2qpPbl2QLe8pRo71gG5Cg?both#117-T-Flip-Flop "Chap 11 - T flip-flop"), Q^+^=T ⊕ Q
:arrow_down:
Q=0 → T = Q^+^
Q=1 → T = Q^+^'
| T   | Q   | Q^+^ |
| --- | --- | ---- |
| 0   | 0   | 0    |
| 1   | 0   | 1    |
| 0   | 1   | 1    |
| 1   | 1   | 0    | 
so for input map
- 在 0 的 half: 照抄  
- 在 1 的 half: 取 complement (0, 1互換)，X照抄  (for T flip-flops)(bc XOR)  
- see [12.6](#126-Summary) for summary
![](https://i.imgur.com/A1EQibx.png)

<!-- ### counter using T flip-flops -->
再根據以上式子畫出
![](https://i.imgur.com/5WQLZG2.png)

(falling edge)
![](https://i.imgur.com/2Lsyue4.png)

if CBA=001 and T~C~T~B~T~A~=110 then
![](https://i.imgur.com/Rr8DsdF.png)

### D flip-flop implementation
---
***這部分跟上面一樣***

假設有一個東西的 transition map 長這樣
![](https://i.imgur.com/dmsKIy4.png)
可根據這個 map 反向做出他的 circuit

畫出 transition table
![](https://i.imgur.com/hSGSLKB.png)
根據上表填出 next-state map
![](https://i.imgur.com/SAo9MNh.png)

---
得出 input map
- D~C~ = C^+^ = B'
- D~B~ = B^+^ = C + BA'
- D~A~ = A^+^ = CA' + BA' = A'(C + B)

做出 circuit
![](https://i.imgur.com/sKVOI8C.png)

<!-- 12.4 再下面似乎沒教 -->

## 12.5 Counter Design Using S-R and J-K Flip-Flops
<!-- <a name="125"></a> -->
### use S-R flip-flops
---
***這部分跟上面一樣***

假設有一個東西的 transition map 長這樣
![](https://i.imgur.com/dmsKIy4.png)
可根據這個 map 反向做出他的 circuit

---
S-R flip-flop: Q^+^ = S + R'Q
從原本的 truth table (a) 整理成 (c\)
![](https://i.imgur.com/VYxIcgM.png)
根據 (c\) 填出下表
![](https://i.imgur.com/8bmuBWe.png)

再根據上表畫出 next-state maps & input maps (equations)
![](https://i.imgur.com/ACgm9mi.png)
![](https://i.imgur.com/vPPgP1Q.png)

circuit
![](https://i.imgur.com/yU3gQX6.png)

### use J-K flip-flops
---
***這部分跟上面一樣***

假設有一個東西的 transition map 長這樣
![](https://i.imgur.com/dmsKIy4.png)
可根據這個 map 反向做出他的 circuit

---
[J-K flip-flop](https://hackmd.io/s2qpPbl2QLe8pRo71gG5Cg?both#116-J-K-Flip-Flop): P = JQ' + K'Q
其實可以直接寫出 (c\)
![](https://i.imgur.com/NdSAqWW.png)
![](https://i.imgur.com/IDH86Wx.png)

![](https://i.imgur.com/pEr7zwl.png)
![](https://i.imgur.com/clFGVC5.png)

circuit
![](https://i.imgur.com/cyKDcTH.png)

## 12.6 Summary
<!-- ![課本 ver.](https://i.imgur.com/IGrNyIE.png) -->
++做 input map from next-state map++
T flip-flop: 0 的 half 照抄，1 的 half 相反
D flip-flop: 一模一樣
S-R、J-K flip-flop 不用看 next-state map，直接對下表
![](https://i.imgur.com/54yRi9T.png)

---
參考用
![](https://i.imgur.com/pzzrQGx.png)

---


## Ch11 & Ch12 Problems
11.2(a)(b)
![](https://i.imgur.com/b847k6A.png)
![](https://i.imgur.com/lVYfJaP.png)
![](https://i.imgur.com/tnWfpHN.png)

11.10(a)(c\)
![](https://i.imgur.com/1JMq8a2.png)
![](https://i.imgur.com/2AlTPG1.png)

11.13(a)(b)
![](https://i.imgur.com/ROOET1C.png)
![](https://i.imgur.com/mMKg14s.png)

11.21
![](https://i.imgur.com/dhtI8Ks.png)
![](https://i.imgur.com/7Firbik.png)

11.24
![](https://i.imgur.com/iMRPFZc.png)
![](https://i.imgur.com/9JEjzIa.png)
**注意**
rising edge trigger: 該 input=0→1 時trigger
so Q~0~ 看 Clock=0→1, Q~1~ 看 Q~0~=0→1, Q~2~ 看 Q~1~=0→1


12.4
![](https://i.imgur.com/rQeru5U.png)
![](https://i.imgur.com/D1KE2h9.png)
<img src="https://i.imgur.com/KSp95Te.png" height="240">

12.6
![](https://i.imgur.com/pxyNaSp.png)
![](https://i.imgur.com/j3J0RHe.png)

12.12
![](https://i.imgur.com/AwWkX3e.png)
![](https://i.imgur.com/6VfyYhM.png)

12.20
![](https://i.imgur.com/U4o8Foj.png)
![](https://i.imgur.com/HJaQc3Z.png)
![](https://i.imgur.com/Cjse3ub.png)

12.37
![](https://i.imgur.com/fywIRzE.png)
![](https://i.imgur.com/bv3qSZP.png)
![](https://i.imgur.com/IV65dZQ.png)



