---
###### tags: `College Notes`,`SCLD`
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# Chap 12 Registers and Counters
## 12.1 Registers and Register Transfers
 (falling-edge)
Load = 0 → register not clocked → stable
Load = 1 → clock → flip-flop
if Load = 1 and falling edge, Q=0000→1101

better, no timing problem (因為直接接)

bus
<img src="https://i.imgur.com/QrRf0J5.png" height="200">

### Data Transfer Between Registers
- E~n~=1 → Register A enabled
- E~n~=0 → Register B enabled

for D₁: En=1 → D₁=A₁, En=0 → D₁=B₁
for D₂ 同理

enabled when En=0

EnA=0 → A enabled
LdG=1 → load into G
EF=00 → A
EF=01 → B
EF=10 → C
EF=11 → D

### accumulator
sum 輸出到 D 被 flip-flop 擋住, clock edge 時再 pass to Q 加回去 (:arrow_right: 累加)
→ 讓大家同時進行累加

**adder cell with multiplexer**
Ld(Load) = 0 → 同上圖的 FA
Ld = 1 → 初始值

## 12.2 Shift Registers
shift=1 → data right shift
clock=0→1 → SI pass to Q₃, Q₃ pass to Q₂, .....
(if 虛線 connects → end around shift)

SI=1,1,0,1
Q[3..0]=0101→1010→1101→0110→1011

8-bit shift register
[SR flip-flop](https://hackmd.io/s2qpPbl2QLe8pRo71gG5Cg?view#115-S-R-Flip-Flop):

SR=00 → no change
SR=01 → Q=0
SR=10 → Q=1
SR=11 → not allowed

今 S=SI, R=SI'
so 每個都變 D flip-flop

shifts in {→| 7 clock periods later}shifts out

can all 4 bits can be loaded in & read out simultaneousely
<!-- Sh=1 → everone shifts right
Sh=0, L=1 → D loaded
Sh=0, L=0 → no change -->

Q₃⁺ = Sh′ · L′ · Q₃ + Sh′ · L · D₃ + Sh · SI
Q₂⁺ = Sh′ · L′ · Q₂ + Sh′ · L · D₂ + Sh · Q₃
Q₁⁺ = Sh′ · L′ · Q₁ + Sh′ · L · D₁ + Sh · Q₂
Q₀⁺ = Sh′ · L′ · Q₀ + Sh′ · L · D₀ + Sh · Q₁

timing diagram when SI=0 and D[3..0]=1011
(falling edge)

### 3-bit shift register with inverted feedback
00{++0++|→1 & 左插} → 10++0++ → 110 → ...
circuit that cycles → counter

<!-- 似乎沒教 -->
<!-- general shift register counter
 -->

## 12.3 Design of Binary Counters
#### use T flip-flops
T flip-flop: Q⁺=T⊕Q[^[1]](https://hackmd.io/s2qpPbl2QLe8pRo71gG5Cg?both#117-T-Flip-Flop "Chap 11 - T flip-flop")
C只有在 A=B=1 時會進位 so T~C~=AB
<!-- CBA=000 → 001 (bc T_A=1) → 010 :arrow_down: -->
C^+^ = C ⊕ T~C~ so：
C != C^+^ 代表 T~C~ = 1
C = C^+^ 代表 T~C~ = 0
:arrow_double_down:

T~C~=AB
T~B~=A
T~A~=1

#### 以 D flip-flop 取代 T flip-flop
(等效)
D_A = A⁺ = A ⊕ 1 = A'
D_B = B⁺ = B ⊕ A
D_C = C⁺ = C ⊕ BA

### up-down binary counter
D_A = A⁺ = A ⊕ (U + D) (A~U~ = A~D~)
D_B = B⁺ = B ⊕ (UA + DA′) (B~U~ = B~D~')
D_C = C⁺ = C ⊕ (UBA + DB′A′) (B~U~A~U~ = (B~D~A~D~)')
use D flip-flops

### laodable counter with clock enable
<img src="https://i.imgur.com/3D6l3nl.png" height="150">

Ct(count)=1 → next state ([original bianary counter](#以-D-flip-flop-取代-T-flip-flop))
Ld=1(→Ld'=0) → D go through XOR
<!--  -->

A⁺ = D_A = (Ld′·A + Ld ·D_Ain) ⊕ Ld′·Ct
B⁺ = D_B = (Ld′·B + Ld ·D_Bin) ⊕ Ld′·Ct · A
C⁺ = D_C = (Ld′·C + Ld ·D_Cin) ⊕ Ld′·Ct · B · A

## 12.4 Counters for Other Sequences
### T flip-flop iplementation
---
假設有一個東西的 transition map 長這樣
可根據這個 map 反向做出他的 circuit

畫出 transition table
根據上表填出 next-state map

---

for [T flip-flop](https://hackmd.io/s2qpPbl2QLe8pRo71gG5Cg?both#117-T-Flip-Flop "Chap 11 - T flip-flop"), Q^+^=T ⊕ Q
:arrow_down:
Q=0 → T = Q^+^
Q=1 → T = Q^+^'
| T | Q | Q^+^ |
| --- | --- | ---- |
| 0 | 0 | 0 |
| 1 | 0 | 1 |
| 0 | 1 | 1 |
| 1 | 1 | 0 |
so for input map
- 在 0 的 half: 照抄
- 在 1 的 half: 取 complement (0, 1互換)，X照抄 (for T flip-flops)(bc XOR)
- see [12.6](#126-Summary) for summary

<!-- ### counter using T flip-flops -->
再根據以上式子畫出

(falling edge)

if CBA=001 and T~C~T~B~T~A~=110 then

### D flip-flop implementation
---
***這部分跟上面一樣***

假設有一個東西的 transition map 長這樣
可根據這個 map 反向做出他的 circuit

畫出 transition table
根據上表填出 next-state map

---
得出 input map
- D~C~ = C^+^ = B'
- D~B~ = B^+^ = C + BA'
- D~A~ = A^+^ = CA' + BA' = A'(C + B)

做出 circuit

<!-- 12.4 再下面似乎沒教 -->

## 12.5 Counter Design Using S-R and J-K Flip-Flops
<!-- <a name="125"></a> -->
### use S-R flip-flops
---
***這部分跟上面一樣***

假設有一個東西的 transition map 長這樣
可根據這個 map 反向做出他的 circuit

---
S-R flip-flop: Q^+^ = S + R'Q
從原本的 truth table (a) 整理成 (c\)
根據 (c\) 填出下表

再根據上表畫出 next-state maps & input maps (equations)

circuit

### use J-K flip-flops
---
***這部分跟上面一樣***

假設有一個東西的 transition map 長這樣
可根據這個 map 反向做出他的 circuit

---
[J-K flip-flop](https://hackmd.io/s2qpPbl2QLe8pRo71gG5Cg?both#116-J-K-Flip-Flop): P = JQ' + K'Q
其實可以直接寫出 (c\)


circuit

## 12.6 Summary
<!--  -->
++做 input map from next-state map++
T flip-flop: 0 的 half 照抄，1 的 half 相反
D flip-flop: 一模一樣
S-R、J-K flip-flop 不用看 next-state map，直接對下表

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參考用

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## Ch11 & Ch12 Problems
11.2(a)(b)

11.10(a)(c\)

11.13(a)(b)

11.21

11.24
**注意**
rising edge trigger: 該 input=0→1 時trigger
so Q~0~ 看 Clock=0→1, Q~1~ 看 Q~0~=0→1, Q~2~ 看 Q~1~=0→1

12.4
<img src="https://i.imgur.com/KSp95Te.png" height="240">

12.6

12.12

12.20

12.37