課程資訊&歷屆 (Notion)
Ch1-6 (Notion)
Ch4 Consumers in Marketplace
Ch7 Competition
Ch8 Welfare Economics and the Gains from Trade
Ch9 Knowledge and Information
Ch10 Monopoly
Ch11 Market Power, Colusion, and Obligopoly
Ch12 Game Theory
Ch13 Externality
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Gitlab CICD
Intro
full codes: https://gitlab.com/dlccyes/cicd
What does it do?
Whenever you push code to your gitlab repo, gitlab's CI/CD pipeline would be triggered. In the first step, it will build a docker image and push the docker image to your Google Container Registry (GCR). In the second step, it will push the image to your Google Kubernetes Engine (GKE).
Guides followed
main
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###### tags: `SCLD`
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# Chap 15 Reduction of State Tables State Assignment
## 15.1 Elimination of Redundant States
example from [14.3](https://hackmd.io/LXOP-VITQvud6TBSDE25uA?both#143-Guidelines-for-Construction-of-State-Graphs)
The circuit examines groups of four consecutive inputs and produces an output Z = 1 if the input sequence 0101 or 1001 occurs. The circuit resets after every four inputs.
4 bit → reset → A

H → next state A, output 0
dlccyes changed 6 years agoView mode Like 1 Bookmark
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###### tags: `SCLD`
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# Chap 14 Derivation of State Graphs and Tables
## 14.1 Design of a Sequence Detector
example:
design the circuit so that any input sequence ending in 101 will produce an output Z = 1
coincident with the last 1

*the symbol before the slash is the input and the symbol after the slash is the corresponding output*
#### Mealy machine
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<!-- <img src="https://i.imgur.com/WXhooFk.png" height="110">
<img src="https://i.
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###### tags: `College Notes`,`SCLD`
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# Chap 12 Registers and Counters
## 12.1 Registers and Register Transfers
 (falling-edge)
Load = 0 → register not clocked → stable
Load = 1 → clock → flip-flop
if Load = 1 and falling edge, Q=0000→1101

better, no timing problem (因為直接接)
bus
<img src="https://i.imgur.com/QrRf0J5.png" height="200">
### Data Transfer Between Registers
- E~n~=1 → Register A enabled
- E~n~=0 → Re
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###### tags: `College Notes`,`SCLD`
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# Chap 11 Latches and Flip-flops
flip-flop: only response to a ==clock input== (but not a data input)
<img src="https://i.imgur.com/o0ZQV5r.jpg" height = "300">
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bc propagation
odd number of inverters → oscillate
## 11.2 S-R Latch
### original NOR S-R Latch

左上 → switch S → 右上 → switch S → 左下 → switch R → 右下
![](https://i.imgur.com/Nm
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