dlccyes

@dlcc

https://www.derricklin.net

Joined on Nov 24, 2019

  • Index 22/05/16 Notes 2021-2 Semester Review 22/09/13 Notes 22/09/20 Notes 22/09/27 Notes 22/10/11 Notes 22/11/22 Notes
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  • 課程資訊&歷屆 (Notion) Ch1-6 (Notion) Ch4 Consumers in Marketplace Ch7 Competition Ch8 Welfare Economics and the Gains from Trade Ch9 Knowledge and Information Ch10 Monopoly Ch11 Market Power, Colusion, and Obligopoly Ch12 Game Theory Ch13 Externality
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  • === 交換電路與邏輯設計 電路學 生物科學通論 機率與統計 普物報告-核融合發電 大學國文一 一 莊子 & 史記 個體經濟學 經濟貨幣整合:歐元區理論與實證
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  • Gitlab CICD Intro full codes: https://gitlab.com/dlccyes/cicd What does it do? Whenever you push code to your gitlab repo, gitlab's CI/CD pipeline would be triggered. In the first step, it will build a docker image and push the docker image to your Google Container Registry (GCR). In the second step, it will push the image to your Google Kubernetes Engine (GKE). Guides followed main
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  • Ch1 前導 Ch2 金融體系概要 Ch3 貨幣與支付系統 Ch4 現值與利率 Ch5 債券市場與利率的決定 Ch6 利率風險結構和期限結構 Ch7 金融體系的經濟分析 Ch8 銀行的經營管理 Ch9 台灣銀行業的結構與發展
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  • 108 (大一) Notes
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  • --- ###### tags: `College Notes`,`Biology` --- Biology === - [楊健志](/eQtXsS2VQDmzm8x5fdDm8A) - [莊曜宇](/DGxooqWpQeixMQaCpxuNsw?view)
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  • --- dir: ltr tags: Biology, College Notes description: 生物科學通論 4th 考試 (期末考) image: https://i.imgur.com/s1rmE4c.png title: 莊曜宇 --- **<font size=7>莊曜宇</font>** --- >[time=Saturday Jan, 04, 2020] >[time=Wednesday Jan, 08, 2020] <iframe width="500" height="150" scrolling="no" frameborder="no" allow="autoplay" src="https://w.soundcloud.com/player/?url=https%3A//api.soundcloud.com/tracks/668254808&color=%23eb734c&auto_play=false&hide_related=false&show_comments=false&show_user=true&show_reposts=false
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  • --- tags: SCLD --- # 交電歷屆期末考 [交電共同網頁](https://sites.google.com/access.ee.ntu.edu.tw/scld-2019-fall/announcements?authuser=0 "哼哼") ## [2018](https://drive.google.com/file/d/1clf9ebChvjSuwf3KKtCLlWZJbg0Q45U9/view "^_^") ### Problem 1 ![](https://i.imgur.com/1bONUMp.png) ### Problem 2 ![](https://i.imgur.com/zw5vIgv.png) ### Problem 3 ![](https://i.imgur.com/4DcVLdX.png) ### Problem 4 ![](https://i.imgur.com/a5EzKKx.png) ![](https://i.imgur.com/1S2A7ML.png) ![](https://i.imgur.com/6RNuYgh.png) ![]
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  • --- tags: SCLD --- # SCLD <!-- - [交電共同網頁](https://sites.google.com/access.ee.ntu.edu.tw/scld-2019-fall/) --> - [Chap 11 Latches and Flip-flops](/s2qpPbl2QLe8pRo71gG5Cg) - [Chap 12 Registers and Counters](/8eb5wN-DRMSlXscMArBhsg) - [Chap 13 Analysis of Clocked Sequential Circuits](/80UWJzSeQgitwy7xeCcaMg) - [Chap 14 Derivation of State Graphs and Tables](/LXOP-VITQvud6TBSDE25uA) - [Chap 15 Reduction of State Tables State Assignment](/96dmXAHcRlee18z2vBCadQ) - [Chap 16 Sequential Circuit Design](/
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  • --- ###### tags: `SCLD` --- # Chap 16 Sequential Circuit Design ## 16.2 BCD to excess-3 excess-3:+3 0-9 → 3-12 ![](https://i.imgur.com/vWjRFcf.png) ![](https://i.imgur.com/M9DQT05.png) e.g. t~2~ 01 X=1 → 101 (補在左邊) 去對上表 BCD,對應到同列 Z 的 t~2~ → Z = 0 <!-- handsomejingyuan --> <!-- {黃靖元|大帥哥} --> ![](https://i.imgur.com/qbRkppS.png) ![](https://i.imgur.com/agDs5zz.png) assign 值時 (for the purpose of 比較好圈): - previous state 一樣的放在一起 (e.g. H&M 在一起) - output 一樣的放在一起 <!-- FIGURE 16-2 --
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  • --- ###### tags: `SCLD` --- # Chap 15 Reduction of State Tables State Assignment ## 15.1 Elimination of Redundant States example from [14.3](https://hackmd.io/LXOP-VITQvud6TBSDE25uA?both#143-Guidelines-for-Construction-of-State-Graphs) The circuit examines groups of four consecutive inputs and produces an output Z = 1 if the input sequence 0101 or 1001 occurs. The circuit resets after every four inputs. 4 bit → reset → A ![](https://i.imgur.com/K7zy37c.png) H → next state A, output 0
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  • --- ###### tags: `SCLD` --- # Chap 14 Derivation of State Graphs and Tables ## 14.1 Design of a Sequence Detector example: design the circuit so that any input sequence ending in 101 will produce an output Z = 1 coincident with the last 1 ![](https://i.imgur.com/SykESm6.png) *the symbol before the slash is the input and the symbol after the slash is the corresponding output* #### Mealy machine <!-- partial --> <!-- <img src="https://i.imgur.com/WXhooFk.png" height="110"> <img src="https://i.
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  • --- ###### tags: `College Notes`,`SCLD` --- # Chap 12 Registers and Counters ## 12.1 Registers and Register Transfers ![](https://i.imgur.com/UdHJzNd.png) (falling-edge) Load = 0 → register not clocked → stable Load = 1 → clock → flip-flop if Load = 1 and falling edge, Q=0000→1101 ![](https://i.imgur.com/UwyhHTH.png) better, no timing problem (因為直接接) bus <img src="https://i.imgur.com/QrRf0J5.png" height="200"> ### Data Transfer Between Registers - E~n~=1 → Register A enabled - E~n~=0 → Re
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  • --- ###### tags: `College Notes`,`SCLD` --- # Chap 11 Latches and Flip-flops flip-flop: only response to a ==clock input== (but not a data input) <img src="https://i.imgur.com/o0ZQV5r.jpg" height = "300"> <!-- ![](https://i.imgur.com/o0ZQV5r.jpg) --> ![](https://i.imgur.com/Iss4GTY.png) bc propagation odd number of inverters → oscillate ## 11.2 S-R Latch ### original NOR S-R Latch ![](https://i.imgur.com/5EquyQw.png) 左上 → switch S → 右上 → switch S → 左下 → switch R → 右下 ![](https://i.imgur.com/Nm
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  • --- ###### tags: `SCLD` --- # Chap 13 Analysis of Clocked Sequential Circuits ## 13.1 A Sequential Parity Checker 奇數個 1 → 1 偶數個 1 → 0 出錯 → 0→1 or 1→0 → parity 改變 → 知道出錯 ![](https://i.imgur.com/sQfTMWZ.png) 累積 input 偶數 → Z=0 累積 input 奇數 → Z=1 ![](https://i.imgur.com/U6mBJ5I.png) ![](https://i.imgur.com/bpqMrY3.png) ![](https://i.imgur.com/yt6w0lT.png) ![]() <img src="https://i.imgur.com/U4CjJrZ.png" height="120"> ## 13.2 Analysis by Signal Tracing and Timing Charts The state graph for a <font
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  • --- ###### tags: `College Notes`,'Biology' --- # 楊健志 solvent: 溶劑 ==化學分子記起來== --- [TOC] --- ## 1. Biology and its Themes emergent properties:只有系統有,而單體沒有的屬性 蛋白質錯誤折疊,沈澱,造成疾病 (阿茲海默症、狂牛症) genomics 基因組學 proteomics 蛋白質組學 負回饋較常見 insulin 胰島素 genus 屬 genus name & species name protist 原生生物 bacteria, archaea, protist, fungi, plant, animal inductive reasoning 歸納法 deductive reasoning 演繹法 ## 2. Atoms and Molecules parasite 寄生蟲 trace element 稀有元素 isotopes 同位素 electron shell 電子殼層 valence electr
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