---
# System prepended metadata

title: Combinational and Sequential Circuit
tags: [Digital IC Design]

---

# Combinational and Sequential Circuit
###### tags: `Digital IC Design`

[回到主頁面](https://hackmd.io/@derek8955/BkK2Nb5Jo/https%3A%2F%2Fhackmd.io%2FdpcBlBL8TlShpQ-wSi9Quw)

Combinational 的電路可以使用 behavioral modeling 或 dataflow modeling 撰寫。如果要設計一加法器，則可使用以下兩種方法:


```verilog=
// adder with dataflow modeling
module COMB( result, a, b, );
    
input a, b;
output [1:0] result;

assign result = a + b;    
    
endmodule

// adder with behavioral modeling
module COMB( result, a, b, );
    
input a, b;
output [1:0] result;
    
always @( * ) result = a + b;    
    
endmodule
```

Sequential 的電路為 clock trigger，所以自然只能使用 behavioral modeling:
```verilog=
// 簡單的 counter，電路圖如下
module SEQ( cnt, clk, rst_n );
    
input clk, rst_n;    
output [3:0] cnt;
    
always @( posedge clk or negedge rst_n ) begin
    if( !rst_n ) cnt <= 0;
    else cnt <= cnt + 1;
endmodule
    
```

|![](https://i.imgur.com/nFvSADq.png)|
|:---:|
| 4 bit counter |
|Ref: https://zh.m.wikipedia.org/zh-tw/%E8%AE%A1%E6%95%B0%E5%99%A8|

### <font color = "blue">Appendix </font>

回顧 [04 - data type](https://hackmd.io/PUFV4TJWR46sFqgljeOOJA)，有說到 **reg** 這個 data type 不是指真正的暫存器，這邊舉個例子會更加清楚。

```verilog=
module COMB( a, b, c );
input a, b;
output reg c;

always @( * ) begin
    c = a | b;
end
    
endmodule

module SEQ( a, b, c);
input a, b;
output reg c;

always @( posedge clk ) begin
   c <= a | b; 
end
    
endmodule
```

|![](https://i.imgur.com/blyigLE.png)| ![](https://i.imgur.com/Vgec0zb.png) |
|:---:|:---:|
| COMB module | SEQ module |
| Combinational circuit | Sequential circuit |

> COMB module 中的 c 雖被宣告成 reg ， 但合成出的電路卻只是簡單的 or gate 

