---
# System prepended metadata

title: 常數的定義
tags: [Digital IC Design]

---

# 常數的定義
###### tags: `Digital IC Design`

[回到主頁面](https://hackmd.io/@derek8955/BkK2Nb5Jo/https%3A%2F%2Fhackmd.io%2FdpcBlBL8TlShpQ-wSi9Quw)

Verilog 常用的兩種宣告為常數的方法:
1.  `define 
2.  parameter 

```verilog=
// `define
`define WIDTH 4
module MUX2to1(
// Output Signals
    out,
// Input Signals
    a,
    b,
    sel
);
input a, b, sel;
output out;

wire [`WIDTH-1:0] tmp; // wire [3:0] tmp;
 
endmodule

------------------------------------------------------------------------------------

// parameter
module MUX2to1(
// Output Signals
    out,
// Input Signals
    a,
    b,
    sel
);
input a, b, sel;
output out;
    
parameter WIDTH = 4;    

wire [WIDTH-1:0] tmp; // wire [3:0] tmp;
    
endmodule
```