# 常數的定義
###### tags: `Digital IC Design`

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Verilog 常用的兩種宣告為常數的方法:
1. `define
2. parameter

// `define
`define WIDTH 4
module MUX2to1(
// Output Signals
    out,
// Input Signals
    a,
    b,
    sel
);
input a, b, sel;
output out;

wire [`WIDTH-1:0] tmp; // wire [3:0] tmp;
 
endmodule

------------------------------------------------------------------------------------

// parameter
module MUX2to1(
// Output Signals
    out,
// Input Signals
    a,
    b,
    sel
);
input a, b, sel;
output out;
    
parameter WIDTH = 4;    

wire [WIDTH-1:0] tmp; // wire [3:0] tmp;
    
endmodule