---
# System prepended metadata

title: APR Script
tags: [Digital IC Design]

---

# APR Script
###### tags: `Digital IC Design`

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`Process Node : TSMC_90GUTM`

- 1. Open Innovus
% innovus

- 2. Import Design

- 3. Global Net Connect

innovus # >clearGlobalNets
innovus # >globalNetConnect VDD -type pgpin -pin VDD -instanceBasename *
innovus # >globalNetConnect VSS -type pgpin -pin VSS -instanceBasename *

- 4. Save File 

File name: DBS/init

- 5. Specifying Scan Chain

innovus # > specifyScanChain scan1 -start ipad_SCAN_IN/C -stop opad_SCAN_OUT/I

innovus # > scanTrace

- 6. Floorplan

|Floorplan → Specify Floorplan…|
|:---:|
|![](https://i.imgur.com/UzkFsoV.png)|

> Skip step 7 if your design doesn't have any soft/hard macro ...
- 7. Plan Design

Floorplan → Automatic Floorplan → Plan Design…

- 8. Edit Halo

|Floorplan → Edit Floorplan → Edit Halo |
|:---:|
|![](https://i.imgur.com/GR8m0jG.png)|

- 9. Save File

File name: DBS/floorplan

- 10. Power Planning

    - Add Power Rings
        Power → Power Planning → Add Ring…
    
    |![](https://hackmd.io/_uploads/rJCOzEBqn.png)|
    |:---:|
    |![](https://i.imgur.com/lTUrxx4.png)|
    
    - Connect core power pad to ring 
        Route → Special Route…
    
    |![](https://i.imgur.com/PWZvpnZ.png)|
    |:---:|
    |![](https://i.imgur.com/Pm9AQnW.png)|
    |![](https://i.imgur.com/wnYsfBC.png)|
    
    - Add Power Stripe
        Power → Power Planning → Add Stripes…
        
    |垂直 stripe|
    |:---:|
    |![](https://i.imgur.com/hzGl14H.png)| 
    |水平 stripe|
    |![](https://i.imgur.com/rtIcyNZ.png)|
    
    - Add Follow Pin
        Route → Special Route…
        
        In Basic Panel → Choose Follow Pins
        In Via Generation Panel → Make Via Connections To → Core Ring, Stripe, Block Ring
        > 無 hard macro 不用勾選 Block Ring

- 11. Add IO Filler
    innovus # > cp /cad/CBDK_TSMC90...../CIC/SOCE/addIofiller.cmd .
    innovus # > source addIofiller.cmd

- 12. Add Routing Blockage

    - 12.1 Save 繞線資訊(DEF)
        File → Save → DEF …
    - 12.2 Copy info.
    #> cp /cad/CBDK_TSMC90...../CIC/SOCE/bond_pads/* .
    - 12.3 Source 
    innovus # > perl ./addbonding_for_90_v3.pl CHIP.def
    innovus # > source addRouteBlk.cmd

- 13. Verify Geometry & Connectivity
    - 13.1 Verify geometry
        innovus # > verify_drc 
    - 13.2  Verify connectivity
        Verify → Verify Connectivity …
        |![](https://i.imgur.com/WEEE7Bn.png)|
        |:---:|

- 14. Save File 

File name: DBS/powerplan
   
- 15. Placement

innovus # > createBasicPathGroups -expanded
innovus # > get_path_groups
innovus # > place_opt_design

- 16. Report Timing & ECO

innovus # > timeDesign -preCTS

確認所有 timing path 的 slack 都是正的
如果有任何一條違例，對 design 優化

innovus # > optDesign -preCTS

- 17. Save File 

File name: DBS/place

- 18. Clock Tree Synthesis (CTS)

innovus # > cp CHIP.sdc ./CHIP_cts.sdc

開啟 CHIP_cts.sdc ， 把 set_ideal_network, clock_uncertanty與 clock_latency 移除

innovus # > update_constraint_mode -name func_mode -sdc_files ./CHIP_cts.sdc
innovus # > create_ccopt_clock_tree_spec -file ./ccopt.spec
innovus # > source ./ccopt.spec
innovus # > ccopt_design -cts

>　See DOC( page3)

- 19. Report Timing & ECO 
    
innovus # > timeDesign -postCTS
innovus # > timeDesign -postCTS -hold

- 20. Add Tie Hi/Lo cell
    
|Place → Tie HI/LO → Add…|
|:---:|
|![](https://i.imgur.com/kS00H2g.png)|

- 21. Routing
    
|Route → NanoRoute → Route|
|:---:|
|![](https://i.imgur.com/Bs1ouCa.png)|

- 22. Save File 

File name: DBS/route

- 23. Report Timing &ECO

in-Place Optimization – After Detail Route

|Tools → set Mode → Specify Analysis Mode…|
|:---:|
|![](https://i.imgur.com/miOwe2W.png)|

innovus # > timeDesign -postRoute
innovus # > timeDesign -postRoute -hold

- 24. Save File 

File name: DBS/route

- 25. Add Core Filler cells
    innovus # > addFiller -cell FILL8 FILL64 FILL4 FILL32 FILL2 FILL1 FILL16 -prefix FILLER

- 26. Add Dummy Metal
    
|Route → Metal Fill → Setup…|
|:---:|
|![](https://i.imgur.com/6gYzeLr.png)|
|Route → Metal Fill → Add…|
|![](https://i.imgur.com/BzjK1rz.png)|
   
- 27. Verify Geometry & Connectivity & Process Antenna

    - 27.1 Verify geometry
        innovus # > verify_drc
    - 27.2 Verify connectivity
        Verify → Verify Connectivity …  
    - 27.3 Verify process antenna
        Verify → Verify Process Antenna…

- 28. Output Data
    
    - 28.1 File → Save → Netlist…
        - Include Intermediate Cell Definition
        - Include Leaf Cell Definition
    - 28.2 Add Bounding Pad
         innovus # > source addbond.cmd
    - 28.3 File → Save Design…
        DBS/final
    - 28.4 Write SDF
     innovus # > setAnalysisMode -analysisType bcwc  
     innovus # > write_sdf -max_view av_func_mode_max -min_view av_func_mode_min -edges noedge -splitsetuphold -remashold -splitrecrem -min_period_edges none CHIP.sdf              
    - 28.5 Stream Out
        - 28.5.1 Copy info.
            #> cp /cad/CBDK_TSMC90…/CIC/Phantom/* .
            #> cp /cad/CBDK_TSMC90…/CIC/SOCE/streamOut.map
        - 28.5.2 Set Stream Output Mode
            innovus # > setStreamOutMode -specifyViaName default -SEvianames false -virtualConnection false -uniquifyCellNamesPrefix false -snapToMGrid false -textSize 1 - version 3
        - 28.5.3 Stream Output
            innovus # > streamOut CHIP.gds -mapFile ./streamOut.map -merge {tpbn90v_9lm_cic2.gds tpzn90gv3_9lm_cic.gds tsmc090hvt_macro.gds tsmc090nvt_macro.gds} -stripes 1 -units 1000 -mode ALL
    


### <font color = "blue"> Brief Flow </font>

Import Design → Global Net Connect → Save File → Specifying Scan Chain → Floorplan → Save File → Power Planning(Ring, Block Ring, Stripe, Pad, Follow) → Add IO Filler → Add Routing Blockage → Verify Geometry & Connectivity → Save File → Placement → Report Timing & ECO → Save File → CTS → Report Timing & ECO → Add Tie Hi/Lo cell → Routing → Save File → Report Timing &ECO → Save File → Add Core Filler → Add Dummy Metal → Verify Geometry & Connectivity & Process Antenna → Output Netlist → Add Bounding Pad → Save File → Write SDF → Stream Out