# Tetramax
###### tags: `Digital IC Design`

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1. Open Tetramax
#> tmax &

> Fill the scripts in “BUILD>” column

2. Set Message
tmax #> set_messages -log chip.log -replace

3. Read Netlist
tmax #> read_netlist tsmc18.v
> Choosing by your process node

tmax #> read_netlist chip_scan.vg

4. Build the fault simulation model
tmax #> run_build_model <font color = "RED">TOP_MODULE_NAME</font>

5. Run design rule checking using STIL procedure file
tmax #> set_rules C4 ignore
tmax #> run_drc chip_scan.spf

6. Add fault list
tmax #> add_faults -all

7. Run ATPG
tmax #> set_pat -internal
tmax #> run_atpg -auto
tmax #> set_faults -fault_coverage
tmax #> set_faults -summary verbose
tmax #> report_summaries
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