# Design Compiler for DFT(Design for Testability)
###### tags: `Digital IC Design`

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> ScanChain: 1 條

- 1. 開啟 design compiler
#> dc_shell

- 2. Read DDC file

- 3. Create test protocol and Perform pre-DFT DRC
dc_shell #> create_port -dir in SCAN_IN
dc_shell #> create_port -dir out SCAN_OUT
dc_shell #> create_port -dir in SCAN_EN
dc_shell #> set_dft_signal -view exist -type ScanClock -timing {45 55} -port clk
dc_shell #> set_dft_signal -view exist -type Reset -active_state 1 -port reset
dc_shell #> create_test_protocol
dc_shell #> dft_drc

- 4. Perform test-ready compile
dc_shell #> compile -scan -map_effort high -area_effort high -boundary_optimization

- 5. Specify test components
dc_shell #> set_scan_configuration -chain_count 1 -clock_mixing mix_clocks_not_edges -internal_clocks single -add_lockup false
dc_shell #> set_dft_signal -view spec -port SCAN_IN -type ScanDataIn
dc_shell #> set_dft_signal -view spec -port SCAN_OUT -type ScanDataOut
dc_shell #> set_dft_signal -view spec -port SCAN_EN -type ScanEnable
-active_state 1
dc_shell #> set_scan_path chain1 -scan_data_in SCAN_IN -scan_data_out SCAN_OUT

- 6. Insert scan
- 6.1 Confirm the message is correct after previewing the scan synthesis
dc_shell #> preview_dft -show all
- 6.2 Insert
dc_shell #> insert_dft

- 7. Save FIle
- 7.1 Save Netlist
dc_shell #> write -format verilog -hier -out chip_scan.vg
- 7.2 Save SDF
dc_shell #> write_sdf -version 3.0 -context verilog -load_delay cell chip_scan.sdf
- 7.3 Save spf
dc_shell #> write_test_protocol -out chip_scan.spf
> tetra max 所需檔案