---
# System prepended metadata

title: Clock Gating
tags: [Digital IC Design]

---

# Clock Gating
###### tags: `Digital IC Design`

[回到主頁面](https://hackmd.io/@derek8955/BkK2Nb5Jo/https%3A%2F%2Fhackmd.io%2FdpcBlBL8TlShpQ-wSi9Quw)

晶片的功耗主要有兩大類，詳見[Power Issue筆記](https://hackmd.io/@derek8955/BkK2Nb5Jo/https%3A%2F%2Fhackmd.io%2FuOpQP3LeRyOprTDkEmHMGQ)：靜態功耗(Static Power)和動態功耗(Dynamic Power)
- 動態功耗：主要是由於信號的翻轉( 0->1 or 1->0 )從而導致電路內部的寄生RC充放電引起的
- 靜態功耗：則是在非工作狀態下的洩漏電流(Leakage Current)所引起的

### <font color = "blue"> What is clock gating </font>
Clock gating 的概念就是在晶片實際工作過程中，有些 signal 並不需要一直開啟，則可以在不用的時候將 clock signal 關閉。這樣一來 signal 就不再翻轉，從而有效減少 dynamic power

```verilog=
// Clock Gating 概念
assign clk_gating = clk & gating_enable;
always@(posedge clk_gating or posedge reset) begin
    if(reset) ...
    else ...
end
```

### <font color = "blue"> Two method of clock gating </font>
|Gated data, bypass clock|Gated clock, bypass data|
|:---:|:---:|
|![](https://i.imgur.com/eY6X5He.png)|![](https://i.imgur.com/TVLXATe.png)|
| FPGA |ASIC design|

Ref. : https://www.design-reuse.com/articles/23701/power-analysis-clock-gating-rtl.html

:::success
因為 gated data, bypass clock 需要額外的 MUX，area 則相對比較大，所以在 ASIC design 比較偏好使用 Gated clock, bypass data 的方法
:::

### <font color = "blue"> Using latch in clock gating </font>
如果只是在 clock signal 前面簡單加個 and gate 或 or gate 會有以下兩個問題 : 

|![](https://i.imgur.com/B3dxWLe.png)|
|:---:|
|<font color="blue">Problem 1 :</font> 莫名產生一個 edge，導致 timming violation.   [(見 STA) ](https://hackmd.io/@derek8955/BkK2Nb5Jo/https%3A%2F%2Fhackmd.io%2FBOMX17vmRBumB39IhTR3Eg) |
|![](https://i.imgur.com/47jH2Q6.png) |
|<font color="blue">Problem 2 :</font> 如若 awake/sleep 訊號線不乾淨，在傳遞的過程中產生了 glitch ，會將 clock 訊號進而傳送至 cell 的 clock point |
|![](https://i.imgur.com/ap5WViJ.png)|
|<font color = "blue ">Solution : </font>檔一顆 latch|
| Ref. : https://medium.com/mirkat-x-blog/iclab-lab08-note-6e0b1e8686c8|

:::info
- OR gating 的功耗較 AND gating 低
- 為了防止 design compiler 優化 gating circuit，一般會把 gating circuit 寫在另一個檔案
:::

### <font color = "blue"> Implement in verilog </font>
 
https://github.com/derek8955/spring_iclab/tree/master/Lab10
