---
# System prepended metadata

title: Data reuse
tags: [Digital IC Design]

---

# Data reuse
###### tags: `Digital IC Design`

[回到主頁面](https://hackmd.io/@derek8955/BkK2Nb5Jo/https%3A%2F%2Fhackmd.io%2FdpcBlBL8TlShpQ-wSi9Quw)

```verilog=
// data reuse
module example( sel, a, b, c, d, result );
input [3:0] a,b,c,d;
input sel;
output reg [7:0] result;

wire [3:0] tmp_0, tmp_1;
assign tmp_0 = ( sel )? a : b ;
assign tmp_1 = ( sel )? c : d ;
    
always @( * ) begin
    result = tmp_0 * tmp_1;
end
    
endmodule

module example( sel, a, b, c, d, result );
input [3:0] a,b,c,d;
input sel;
output reg [7:0] result;

always @( * ) begin
    if( sel ) result = a * b;
    else result = c * d;
end
    
endmodule
```
|![](https://i.imgur.com/ZNUT9tf.png)|
|:---:|
|乘法器的面積遠大於 MUX，所以在設計電路的時候，要去想怎麼寫 data reuse|

