# Primetime
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1. Open Primtime(pt_shell)
2. Read Technology File
3. Read Design(read_verilog file_name)
4. Set Current Design(current_design YOUR_DESIGN)
5. Link Design，指定要連結的設計名稱(link_design)
6. Read Switching Activity File(read_vcd –strip_path TESTBED/I_YOUR_DESIGN CHIP.vcd)
7. Read Design Constraint File(read_sdc CHIP.sdc)
8. Annotate Delay Information(read_sdf –load_delay net CHIP.sdf)
9. Set transition time(set_input_transition 0.1 [all_inputs])
10. Generate power waveforms，儲存每個時間點下的Power情形(set_power_analysis_options -waveform_interval 1 -waveform_format out -waveform_output fsdb)
11. Update Power and Report Power(update_power、report_power)