# IR-drop Analysis ###### tags: `Digital IC Design` [回到主頁面](https://hackmd.io/@derek8955/BkK2Nb5Jo/https%3A%2F%2Fhackmd.io%2FdpcBlBL8TlShpQ-wSi9Quw) `Process Node : TSMC_90GUTM` 1. Setting Environment - #> mkdir power_log 做 IR drop 分析時會產生很多檔案 - #> innovus restore design File name: DBS/final - Post Simulation 產出波形檔 2. Static Power Analysis - Power → Power Analysis → Setup Click OK - Power → Power Analysis → Run |![](https://i.imgur.com/Wm2ti7E.png)| |:---:| > Dominant Frequency: design frequency > Scope: testbentch module name/instantiation module name |![](https://i.imgur.com/hhhmO5Y.png)| |:---:| |Terminal 顯示 power 數值| 3. Create Power Grid Library - Power → Rail Analysis → Set PG Library Mode |![](https://i.imgur.com/6OZGvmu.png)| |:---:| > Filler Cell Names: FILL1 FILL16 FILL2 FILL32 FILL4 FILL64 FILL8 > Extraction tech file: */SOCE/Firelce/icecaps.tch > LEF Layermap: */SOCE/Firelce/lef.layermap.libgen > Voltage: 該製成的 core VDD - Power → Rail Analysis → Generate PG Library |![](https://i.imgur.com/NgOXfsw.png)| |:---| - Power → Rail Analysis → Set PG Library Mode |![](https://i.imgur.com/Pbidw7D.png)| |:---| - Power → Rail Analysis → Generate PG Library |![](https://i.imgur.com/NgOXfsw.png)| |:---| 4. Rail Analysis - Power → Rail Analysis → Setup Rail Analysis |![](https://i.imgur.com/50FhrF5.png)| |:---:| - Power → Rail Analysis → Run Rail Analysis |![](https://i.imgur.com/H56CFDE.png)| |:---:| click create → Net Name: VDD → Fetch → Save → CHIP_VDD.pp click create → Net Name: VSS → Fetch → Save → CHIP_VSS.pp |![](https://i.imgur.com/VD4ultC.png)| |:---:| |![](https://i.imgur.com/P82sKao.png)| |:---| > Threshold: 5% of core VDD 5. Power IR-drop Result - Power → Report → Power Rail Result |![](https://i.imgur.com/YR5TwPy.png)| |:---:| 勾選 Auto Aplly for Color Scale Click DB Setup |![](https://i.imgur.com/jiEuwUi.png)| |:---:| |![](https://i.imgur.com/an5gSTn.png)| |:---:| Click Result Browser