Digital IC Design
===
###### tags: `Digital IC Design`
Main Page
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- [主頁](https://hackmd.io/@derek8955/BkK2Nb5Jo/https%3A%2F%2Fhackmd.io%2Fc%2FBkK2Nb5Jo%2Fedit%3Fedit)
資料來源
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- TSRI verilog、Logic Synthesis、Innovus
- [design compiler user guide](https://github.com/hyf6661669/Synopsys-Documents/blob/main/Design%20Compiler%20User%20Guide%20Version%20P-2019.03%2C%20March%202019.pdf)
- 交大 ICLAB
- 台大 CVSD
- [Sunburst](http://www.sunburst-design.com/)(推薦大家可以把這個網站上的paper都看過)
也包含了一些個人看法，若有誤請糾正我><
IC 設計流程
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- [Cell Based Design Flow](https://hackmd.io/dAJB6Em_Rle8DsDHhObYEw)
設計環境
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- [Workstation](https://hackmd.io/WMOdFMqvRPOia7YFeQR1fQ)
Basic of Verilog
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- [01 - What is verilog](https://hackmd.io/yaITWjthTfOuBaN01Uy31g)
- [02 - Brief introduction of design modeling](https://hackmd.io/81pBAwAbSqCTw5c0OYlJug)
- [03 - Module](https://hackmd.io/MgrVO039RwuffZK8AAGJLQ)
- [04 - Data type](https://hackmd.io/PUFV4TJWR46sFqgljeOOJA)
- [05 - Simulator](https://hackmd.io/SlNcr6f1SAealfd2w9uFjg)
- [06 - Constant specified](https://hackmd.io/dHJocC7xSLC86QpdaYMyPw)
- [07 - Operator types](https://hackmd.io/O_VRJLHkTJ2ZxghlaY3q5A)
- [08 - Three types of design modeling](https://hackmd.io/2jaC5Z7jS7OXjopgBycDgg)
- [09 - If statement and case statement](https://hackmd.io/tzXPpB_CQO-HW-t7o3-4PQ)
- [10 - Looping statement](https://hackmd.io/VGQckbNDQxCmie7gIxWDIA)
- [11 - Combinational and sequential circuit](https://hackmd.io/Bi9dnZeFRL6RaNagfIzd6w)
- [12 - Assignments](https://hackmd.io/8Y4jiBc-RXaZ0vF73xC6DQ)
- [13 - Instantiation](https://hackmd.io/DUc5Ud-4Sg-OmIbTjeavOw)
Practice
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- [HDLbits](https://hdlbits.01xz.net/wiki/Main_Page)
- [IC contest](https://ruddy-magic-21b.notion.site/2022-IC-637d2313a4dd4a0596fddcdba549fb85)
RTL Coding Style
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- [Synthesizable Code](https://hackmd.io/FJH-ZCimTfqQ7eAQrS27Tg)
- [Coding style](https://hackmd.io/sXEzB8SGRzWQ4v0ib5cFuA)
Advanced RTL Design
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- [Finite State Machine](https://hackmd.io/yUf-cb3tSsqa746uNIzXlg)
- [Data Reuse](https://hackmd.io/I7IW5xABSruvTWsEImCLDA)
- [Pipeline](https://hackmd.io/lmsj4cLzTS-_IUq3GkHo8A)
- [DesignWare](https://hackmd.io/rIFw2ld7TgqSpkCsYAg9Dg)
- [Memory](https://hackmd.io/PND02XmhT-W6kImkduDt2g)
- [Clock gating](https://hackmd.io/WAPcK4cBSImihHWG-3C8mQ)
- [Clock Domain Crossing](https://hackmd.io/BQ8rbz6pSN2wYYt4PcmyKw)
Testbench
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- [Verification](https://hackmd.io/tgbrOAdgQHWb73wO4ORCmQ)
- [Design Environment of Simulation](https://hackmd.io/ucVu6Tt-SQu2SHft7RdU6A)
- [PATTERN](https://hackmd.io/R9ItHZCAQG24DTjckJVyMg#)
- [TESTBED](https://hackmd.io/_ilLPzS1T3-Jp2GKjxiJhw)
Logic Synthesis
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- [Introduction to Synthesis](https://hackmd.io/UDFZsACSSvSlok65jusH2g)
- [Synthesis Flow](https://hackmd.io/on4SdHtHSc2pa9BD8k2u4g)
EDA Tool
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- [ncverilog](https://hackmd.io/mN43E0BdS3mCeOuPppsMhw)
- [nWave](https://hackmd.io/qU_6unOjTa26GqCZvJskaQ)
- [未完成Spyglass]()
- [Design Compiler for Synthesis](https://hackmd.io/-1Qy45OMRXyCay8s3QgzfQ)
- [Design Compiler for DFT](https://hackmd.io/2caYDBM_Tqie7zUKRT1Emg)
- [Tetramax](https://hackmd.io/bvExAUy6Q0S2kDfV38LqwA)
- [Memory Compiler](https://hackmd.io/0BG0fE6vQ3OZXIh15PR4EQ)
- [Primetime](https://hackmd.io/v4feG18XR4aCqnGy9CkrOQ)
- [Innovus](/2hKY-JSoTi6o0w0By4ipVg)
Lab Sharing
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- [NCYU ICLAB](https://github.com/derek8955/spring_iclab)
- [IC Contest](https://github.com/derek8955/ic_contest)
Other
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- [STA](https://hackmd.io/BOMX17vmRBumB39IhTR3Eg)
- [AMBA](https://hackmd.io/smHOkq4dQA-Sr5TqLZqCsg)
- [Power issue](https://hackmd.io/uOpQP3LeRyOprTDkEmHMGQ)
- [Area Estimation](https://hackmd.io/k2u0x1oHRRaoCXR9Xd2MhA)
- [IR-drop Analysis](/klxb1JUaS4eJqrDVT9KXrQ)
- [其他網站](https://hackmd.io/NRYJv6ueRzaP0Sv_Hi64VA)
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