# Assignments ###### tags: `Digital IC Design` [回到主頁面](https://hackmd.io/@derek8955/BkK2Nb5Jo/https%3A%2F%2Fhackmd.io%2FdpcBlBL8TlShpQ-wSi9Quw) assignment 是指賦予 data 數值的方式,下表介紹了三種 assignment : | Procedural assignment | Continuous assignment | Procedural Continuous assignment| | -------- | -------- | -------- | | Behavioral modeling | Dataflow modeling | 這個不常用,不多做介紹 | ### <font color="green"> Continuous assignment </font> Continuous assignment 很簡單,直接使用 assign LHS = RHS 賦值即可 ### <font color="green"> Procedural assignment </font> 又細分成兩項 : | Blocking assignment | Non-blocking assignment | | ------------------- | ----------------------- | | = | <= | | 循序性的執行程式 | 平行式的執行程式 | | 用在 combinational circuit | 用在 sequential circuit | 先用一個例子看一下兩個assignment 之間的差別 : ```verilog= // Blocking always @( posedge clk ) begin b = a; c = b; end // Non-blocking always @( posedge clk ) begin b <= a; c <= b; end ``` |![](https://i.imgur.com/s1iyOpR.png)|![](https://i.imgur.com/XlIDVg8.png)| |:---:|:---:| |Blocking assignment| Non-blocking assignment | combinational circuit 要使用 blocking assignment,sequential circuit 要使用 Non-blocking assignment ```verilog= // 本來是想設計一 2位元 的移位暫存器,但因為使用不正確的 assignment,造成結果有誤 always @( posedge clk ) begin b = a; c = b; end ``` ```verilog= // 使用正確的 assignment always @( posedge clk ) begin b <= a; c <= b; end ``` |![](https://i.imgur.com/JBzWUzj.png)|![](https://i.imgur.com/2M82XMD.png)| |:---:|:---:| |error|correct| :::danger 所以記得要在 sequential circuit 中使用 non-blocking assignment ; combinational circuit 中使用 blocking assignmemt,以免造成合成後的電路與預期不同 :::