# ECE 350 Processor Overview ## Christian Welch ### Design  * Five-Stage Pipelined Processor * Fetch, Decode, Execute, Memory, Write * Registers feed data between each step * 32-bit MIPS-Like Instruction Set Architecture ### Implementation * Followed diagram above * Implemented all arithmetic instructions, including multiplication & division * Implemented load word & store word instructions #### Arithmetic * add, addi, sub, and, or, sll, sra implemented using arithmetic logic unit (ALU) created previously * mult,div * attempted to integrate into existing ALU by assign two remaining ALUOpcodes to multiplication and division, ran into issues * decided to create separate multdiv unit to handle these calculations * mux decides which output- ALU or MULTDIV- to input to execute/memory stage #### Memory * Utilizes same architecture, general data flow as addi instruction * needed to check opcode to determine which registers are input to ALU * opcode also used to toggle data memory write enable #### Control * Did not end up implementing control instructions * Most of hardware implementation would be utilizing muxes to select PC update * would also use opcode to select which mux output to take * Would implement them as follows: | Instruction | Implementation | | ----------- | -------------- | | j T | Set PC to T in XD using mux, flush FD, XD | | jr | Set PC to value in $rd in XD using mux, flush FD, XD | | bne | Assume branch not taken, if $rd != $rs at XD, flush FD, XD, update PC = 1 + PC + N; otherwise continue | | blt | Same as bne | | jal | Set $r31 to input of PC register (PC+1); then same as j T | | bex | Same as bne; if $r30 != 0 at XD, flush FD, XD update PC = T | | setx | Set $r30 = T at XD | #### Bypassing & Stalling * MultDiv Stalling: * multicycle operations - used code below to stop instructions from being processed until operations are completed *  * Bypassing * Used code below to bypass from XM stage to ALU inputs * Unsuccessful, could not narrow down issue *