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# ItC Week 4~6 - Sequential Logic

###### tags: `Intro_to_Comp`

- ## Some Examples

- Finite State Machine
- Markov Model
- Markov model is one kind
- Hidden Markov Model
- RNN & LSTM
- Sequence to Sequence Model

- ## Introduction

- Some definitions
- state : all the necessary information to know a circuit's futrue behavior
- latches and flip-flops : store one bit of state
- synchronous sequential circuits : combinational logic + flip-flops

- ## Latches and Flip-Flops

- Bistable Circuit
- 
- store 1 bit of state
- but there are no input to control the state

- SR(Set/Reset) Latch
- 
- must avoid $S=R=1$ (cause invalid case like $Q = \overline Q$)

- D Latch
- 
- essentialy it is just a modified version of SR latch
- avoids SR latch's problem

- D Flip-flop
- 
- synchronize with clock at the start of 1
- only allow $D$ go through when clock go from 0 to 1 (a.k.a."*edge triggered*")

- D Latch v.s. D Flip-flop
- 
- Be careful with latency in circuits!

- Enabled Flip-flop
- 
- A multiplexer + A D Flip-Flop
- The enable input decide when $D$ should pass through

- Resettable Flip-flop
- If $Reset$ is 1, Q is forced to be 0
- Else, it behaves like a normal D flip-flop

- Settable Flip-flop
- It's like the resettable flip-flop, but is forcing 1

- Memory Register
- Register Implementation

- ## Synchronous Logic Design

- Sequential circuits
- all circuits that are not combinational
- System synchronized to the clock
- Rules
- each element is either a regster or a combinational circuit
- contains at least 1 register
- all element recieve the same clock(no latency)

- ## Finite States Machine

- Next state determined by input and current state
- Moore FSM
- 
- outputs depend on only current state
- Mealy FSM
- 
- outputs depend on current state ***and*** inputs
- **Implementation : Traffic Light**
- **Implementation : Snail**
- Moore Machine Approach
- Mealy Machine Approach
- Time Diagram : Moore v.s. Mealy
- When sychronized to the clock, their outputs might not happen at the same time.
- Because Moore's output happens when entering the state, it will be a bit slower than Mealy's output, which happens when recieve input.

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