---
# System prepended metadata

title: Lab9_CS22b057

---

# Lab 9
Name: SHIVADHARSHAN S
Roll No.: CS22B057

---
## Question 1

**Code:**
ALU 
```verilog=
module ALU(a,b,sel,c);
    parameter n = 4;
    wire [n-1:0] x1,x2,x3,x4;
    input [n-1:0] a;
    input [n-1:0] b;
    input [1:0] sel;
    output [n-1:0] c;
    assign x1 = a+b;
    assign x2 = a-b;
    assign x3 = a&&b; // logical and is && (gives true or false)
    assign x4 = a||b;
    multiplexer mux(x1,x2,x3,x4,sel,c);
endmodule
```
Multiplexer
```verilog=
module multiplexer(x1,x2,x3,x4,sel,c);
    parameter n=4;
    input [n-1:0] x1,x2,x3,x4;
    input [1:0] sel;
    output [n-1:0] c;
    assign c = !sel[0]&!sel[1] ? x1 : sel[0]&!sel[1] ? x2 : !sel[0]&sel[1] ? x3: x4;
endmodule
```
TestBench
```verilog=
module ALU_tb();
    reg [3:0]a,b;
    reg [1:0] sel;
    wire [3:0]c;
    ALU alu(a,b,sel,c);
    
    initial 
        begin
            $monitor("a=%b,b=%b,sel=%b,c=%b",a,b,sel,c);
            a=4'b0100;b=4'b0100;sel='b01;
        #100	a=4'b0100;b=4'b0100;sel='b00;
        #100	a=4'b1000;b=4'b0100;sel='b10;
        #100	a=4'b1000;b=4'b0100;sel='b11;

        end
endmodule
```
**Output:**

[https://hackmd.io/_uploads/HkVsCLY1R.png]::

![Screenshot from 2024-04-07 13-21-01](https://hackmd.io/_uploads/H1VOxCJe0.png)



___

## Question 2
**Code:**

Processor
```verilog=
module processor(input [7:0] instruction,output [7:0] val);
reg [7:0] memory [255:0];
reg [7:0] reg_file [15:0];
reg [7:0] loc;
reg [7:0] vall;

initial begin
    memory[4] <= 8'b00101010;
    reg_file[1] <= 8'b00000001;
end
always @(*) begin
case (instruction[7])
    // do load
    1'b0:begin 
        loc = reg_file[instruction[1:0]] + instruction[4:2];
        reg_file[instruction[6:5]] = memory[loc];
        vall =  memory[loc]; // To show that its working
    end 
    1'b1:begin
        loc = reg_file[instruction[1:0]] + instruction[4:2];
        memory[loc] = reg_file[instruction[6:5]];
        vall =  memory[loc]; // To show that its working
    end
endcase
end
assign val = vall;
endmodule
```
TestBench
```verilog=
module processor_TB();
reg [7:0] instruction;
wire [7:0] val;
processor p(instruction,val);

initial begin
    $monitor("val=%b",val);
    instruction=8'b01001101;
    instruction=8'b10101101;
end
endmodule
```

**Output:**
![Screenshot from 2024-04-07 10-55-33](https://hackmd.io/_uploads/r1qvAsJgC.png)
___

## Question 3

**inscount0.log**

![Screenshot from 2024-04-07 12-58-37](https://hackmd.io/_uploads/S1krj6JgC.png)


**Code:**
```clike=
#include<stdio.h> 

int main(){
    printf("Hello World!!");
}

```
**Output:**
![Instruction Count](https://hackmd.io/_uploads/Bye1j61gR.png)
___