# Lab 10
Name: SHIVADHARSHAN S
Roll No.: CS22B057
---
## Question 1
### ALU
load word and store word use the adder
**Code:**
```verilog=
module ALU(control,input1,input2,out);
input [6:0] control;
input [31:0] input1;
input [31:0] input2;
output [31:0] out;
wire [31:0] mux_input1,mux_input2,mux_input3,mux_input4,mux_input5,mux_input6,mux_input7,mux_input8,mux_input9,mux_input10,mux_input11,mux_input12,mux_input13,mux_input14,mux_input15,mux_input16;
nbitadder adder(input1,input2,mux_input1);
nbitsubtractor subtrator(input1,input2,mux_input2);
nbitxor xorgate(input1,input2,mux_input3);
nbitor orgate(input1,input2,mux_input4);
nbitand andgate(input1,input2,mux_input5);
left_shifter leftshifter(input1,input2,mux_input6);
right_shifter rightshifter(input1,input2,mux_input7);
right_shifter_arith rightshifterarith(input1,input2,mux_input8);
set_less_than setlessthan(input1,input2,mux_input9);
set_less_than_u setlessthanu(input1,input2,mux_input10);
assign mux_input11 =0;
assign mux_input12 =0;
assign mux_input13 =0;
assign mux_input14 =0;
assign mux_input15 =0;
assign mux_input16 =0;
MUX16_1_32 mux(mux_input1,mux_input2,mux_input3,mux_input4,mux_input5,mux_input6,mux_input7,mux_input8,mux_input9,mux_input10,mux_input11,mux_input12,mux_input13,mux_input14,mux_input15,mux_input16,out,control[3:0]);
endmodule
```
Adder
```verilog=
module halfadder(a,b,s,c);
input a,b;
output s,c;
xor(s,a,b);
and(c,a,b);
endmodule
module fulladder(a,b,cin,s,cout);
input a,b,cin;
output s,cout;
wire w1,w2,w3;
halfadder h1(a,b,w1,w2);
halfadder h2(cin,w1,s,w3);
or(cout,w2,w3);
endmodule
module nbitadder(a,b,s);
parameter n=32;
input [n-1:0] a;
input [n-1:0]b;
output [n-1:0] s;
wire [n-1:0] c;
genvar i;
generate
for (i = 0 ;i<n ;i=i+1 )
begin
if (i==0) begin
halfadder f(a[0],b[0],s[0],c[0]);
end
else begin
fulladder f(a[i],b[i],c[i-1],s[i],c[i]);
end
end
endgenerate
endmodule
```
subtractor
```verilog=
module nbitsubtractor(a,b,s);
parameter n=32;
input [n-1:0] a,b;
output [n-1:0] s;
wire [n-1:0] c;
genvar i;
generate
for (i = 0 ;i<n ;i=i+1 )
begin
if (i==0) begin
half_subtractor f(a[0],b[0],s[0],c[0]);
end
else begin
full_subtractor f(a[i],b[i],c[i-1],s[i],c[i]);
end
end
endgenerate
endmodule
module full_subtractor(a,b,bi,y,bo);
input a,b,bi;
output y,bo;
wire w1,w2,w3;
half_subtractor g1(a,b,w1,w2);
half_subtractor g2(w1,bi,y,w3);
or(bo,w2,w3);
endmodule
module half_subtractor(a,b,d,bo);
input a,b;
output d,bo;
xor g1(d,a,b);
wire nota;
not g2(nota,a);
and g3(bo,nota,b);
endmodule
```
bitwise operators
```verilog=
module nbitand(a,b,s);
parameter n=32;
input [n-1:0] a;
input [n-1:0]b;
output [n-1:0] s;
genvar i;
generate
for (i = 0 ;i<n ;i=i+1 )
begin
and uut(s[i],a[i],b[i]);
end
endgenerate
endmodule
module nbitor(a,b,s);
parameter n=32;
input [n-1:0] a;
input [n-1:0]b;
output [n-1:0] s;
genvar i;
generate
for (i = 0 ;i<n ;i=i+1 )
begin
or uut(s[i],a[i],b[i]);
end
endgenerate
endmodule
module nbitxor(a,b,s);
parameter n=32;
input [n-1:0] a;
input [n-1:0]b;
output [n-1:0] s;
genvar i;
generate
for (i = 0 ;i<n ;i=i+1 )
begin
xor uut(s[i],a[i],b[i]);
end
endgenerate
endmodule
```
shifters
```verilog=
module left_shifter(input1,input2,out);
input [31:0] input1;
input [31:0] input2;
output [31:0] out;
wire [31:0] shifted;
genvar i;
generate
for (i = 0; i < 32; i = i + 1) begin
assign shifted[i] = (i < input2) ? 0 : input1[i - input2];
end
endgenerate
assign out = shifted;
endmodule
module right_shifter(input1,input2,out);
input [31:0] input1;
input [31:0] input2;
output [31:0] out;
wire [31:0] shifted;
genvar i;
generate
for (i = 0; i < 32; i = i + 1) begin
assign shifted[i] = (i + input2 > 31) ? 0 : input1[i + input2];
end
endgenerate
assign out = shifted;
endmodule
module right_shifter_arith(input1,input2,out);
input [31:0] input1;
input [31:0] input2;
output [31:0] out;
wire [31:0] shifted;
assign sign = input1[31];
genvar i;
generate
for (i = 0; i < 32; i = i + 1) begin
assign shifted[i] = (i + input2 > 31) ? sign : input1[i + input2];
end
endgenerate
assign out = shifted;
endmodule
```
set less than
```verilog=
module set_less_than_u(input1,input2,out);
input [31:0] input1,input2;
output [31:0] out;
assign out = (input1<input2) ? 1:0;
endmodule
module set_less_than(input1,input2,out);
input [31:0] input1,input2;
output [31:0] out;
assign out = (input1[31] & 1'b1) ? (input2[31] & 1'b1)? input1>input2 ? 1:0 : 1 : (input2[31] & 1'b1) ? 0: input1 < input2 ?1:0;
endmodule
```
MUX
```verilog=
module MUX16_1_32(mux_input1,mux_input2,mux_input3,mux_input4,mux_input5,mux_input6,mux_input7,mux_input8,mux_input9,mux_input10,mux_input11,mux_input12,mux_input13,mux_input14,mux_input15,mux_input16,mux_out,select_lines);
input [31:0] mux_input1,mux_input2,mux_input3,mux_input4,mux_input5,mux_input6,mux_input7,mux_input8,mux_input9,mux_input10,mux_input11,mux_input12,mux_input13,mux_input14,mux_input15,mux_input16;
wire [31:0] mux_input [15:0];
assign mux_input[0] = mux_input1;
assign mux_input[1] = mux_input2;
assign mux_input[2] = mux_input3;
assign mux_input[3] = mux_input4;
assign mux_input[4] = mux_input5;
assign mux_input[5] = mux_input6;
assign mux_input[6] = mux_input7;
assign mux_input[7] = mux_input8;
assign mux_input[8] = mux_input9;
assign mux_input[9] = mux_input10;
assign mux_input[10] = mux_input11;
assign mux_input[11] = mux_input12;
assign mux_input[12] = mux_input13;
assign mux_input[13] = mux_input14;
assign mux_input[14] = mux_input15;
assign mux_input[15] = mux_input16;
output [31:0] mux_out;
input [3:0] select_lines;
genvar i;
generate
for (i=0;i<32;i=i+1) begin
MUX16_1 mux({mux_input[0][i], mux_input[1][i], mux_input[2][i], mux_input[3][i], mux_input[4][i], mux_input[5][i], mux_input[6][i], mux_input[7][i], mux_input[8][i], mux_input[9][i], mux_input[10][i], mux_input[11][i], mux_input[12][i], mux_input[13][i], mux_input[14][i], mux_input[15][i]},mux_out[i],select_lines);
end
endgenerate
endmodule
module MUX16_1(mux_input,mux_out,select_lines);
input [15:0] mux_input;
output mux_out;
input [3:0] select_lines;
wire s0,s1,s2;
wire [1:0] out;
assign s0 = select_lines[3];
MUX8_1 mux161(mux_input[15:8],out[0],select_lines[2:0]);
MUX8_1 mux162(mux_input[7:0],out[1],select_lines[2:0]);
MUX2_1 mux163(out,mux_out,s0);
endmodule
module MUX2_1(mux_input,mux_out,select_lines);
input [1:0] mux_input;
output mux_out;
input select_lines;
wire s0,s1,s2;
not(s0,select_lines);
and(s1,mux_input[0],s0);
and(s2,mux_input[1],select_lines);
or (mux_out,s1,s2);
endmodule
module MUX2_1_inv(mux_input,mux_out,select_lines);
input [1:0] mux_input;
output mux_out;
input select_lines;
wire s0,s1,s2;
not(s0,select_lines);
and(s1,mux_input[0],select_lines);
and(s2,mux_input[1],s0);
or (mux_out,s1,s2);
endmodule
module MUX4_1(mux_input,mux_out,select_lines);
input [3:0] mux_input;
output mux_out;
input [1:0]select_lines;
wire s0,s1;
wire [1:0]out;
assign s0 = select_lines[0];
assign s1 = select_lines[1];
MUX2_1_inv mux41(mux_input[3:2],out[0],s0);
MUX2_1_inv mux42(mux_input[1:0],out[1],s0);
MUX2_1 mux43(out,mux_out,s1);
endmodule
module MUX8_1(mux_input,mux_out,select_lines);
input [7:0] mux_input;
output mux_out;
input [2:0] select_lines;
wire s0,s1,s2;
wire [1:0] out;
assign s0 = select_lines[2];
MUX4_1 mux81(mux_input[7:4],out[0],select_lines[1:0]);
MUX4_1 mux82(mux_input[3:0],out[1],select_lines[1:0]);
MUX2_1 mux83(out,mux_out,s0);
endmodule
```
test_bench
```verilog=
module ALU_tb();
reg [31:0]a,b;
reg [6:0] sel;
wire [31:0]c;
ALU alu(sel,a,b,c);
initial
begin
$monitor("a=%b,b=%b,sel=%b,c=%b",a,b,sel,c);
a=32'b0101;b=32'b0100;sel=7'b00;
#100 a=32'b0101;b=32'b0100;sel=7'b01;
#100 a=32'b0101;b=32'b0100;sel=7'b10;
#100 a=32'b0101;b=32'b0100;sel=7'b11;
#100 a=32'b0101;b=32'b0100;sel=7'b100;
#100 a=32'b0101;b=32'b0100;sel=7'b101;
#100 a=32'b0101;b=32'b0100;sel=7'b110;
#100 a=32'b10000000000000000000010001000001;b=32'b0100;sel=7'b111;
#100 a=32'b10000000000000000000000000000001;b=32'b010;sel=7'b1000;
#100 a=32'b10000000000000000000000000000001;b=32'b010;sel=7'b1001;
end
endmodule
```
**Output:**
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